mirror of
https://github.com/cemu-project/Cemu.git
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eb48b871d8
This reverts commit 657d9f6f431c34ff905436c11817b76e97107a00. Revert "C++-ify GL default shader code" This reverts commit 81a6f92f8d43fdcc344346111fc1ccdf8a534d5d.
390 lines
13 KiB
C++
390 lines
13 KiB
C++
#include "Cafe/OS/common/OSCommon.h"
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#include "Cafe/HW/Latte/ISA/RegDefines.h"
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#include "GX2.h"
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#include "Cafe/HW/Latte/Core/Latte.h"
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#include "Cafe/HW/Latte/Core/LatteDraw.h"
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#include "Cafe/HW/Latte/Core/LattePM4.h"
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#include "GX2_Command.h"
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#include "GX2_State.h"
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#include "Cafe/CafeSystem.h"
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#define GPU7_REG_AREA_SIZE_CONFIG_REG 0xB00
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#define GPU7_REG_AREA_SIZE_CONTEXT_REG 0x400
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#define GPU7_REG_AREA_SIZE_ALU_CONST 0x800
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#define GPU7_REG_AREA_SIZE_LOOP_CONST 0x60
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#define GPU7_REG_AREA_SIZE_RESOURCE 0xD9E
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#define GPU7_REG_AREA_SIZE_SAMPLER 0xA2 // (guessed)
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#define _GX2_CALC_SHADOWMEM_NUM_U32(__v) (((((__v)*4)+0xFF)&~0xFF)/4)
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MPTR gx2CurrentContextStateMPTR = MPTR_NULL;
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typedef struct
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{
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uint32 regOffset;
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uint32 regCount;
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}GX2RegLoadPktEntry_t;
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GX2RegLoadPktEntry_t aluConst_loadPktEntries[1] = // base: 0xC000
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{
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{0, 0x800},
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};
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GX2RegLoadPktEntry_t loopConst_loadPktEntries[1] = // base: 0xF880
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{
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{0, 0x60},
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};
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GX2RegLoadPktEntry_t samplerReg_loadPktEntries[3] = // base: 0xF000
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{
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{0, 0x36},
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{0x36, 0x36},
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{0x6C, 0x36},
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};
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GX2RegLoadPktEntry_t configReg_loadPktEntries[0xF] = // base: 0x2000
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{
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{0x300, 0x6},
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{0x900, 0x48},
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{0x980, 0x48},
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{0xA00, 0x48},
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{0x310, 0xC},
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{0x542, 0x1},
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{0x235, 0x1},
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{0x232, 0x2},
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{0x23A, 0x1},
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{0x256, 0x1},
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{0x60C, 0x1},
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{0x5C5, 0x1},
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{0x2C8, 0x1},
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{0x363, 0x1},
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{0x404, 0x2}
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};
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GX2RegLoadPktEntry_t contextReg_loadPktEntries[0x2D] = // base: 0xA000
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{
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{0x0, 0x2},
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{0x3, 0x3},
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{0xA, 0x4},
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{0x10, 0x38},
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{0x50, 0x34},
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{0x8E, 0x4},
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{0x94, 0x40},
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{0x100, 0x9},
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{0x10C, 0x3},
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{0x10F, 0x60},
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{0x185, 0xA},
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{0x191, 0x27},
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{0x1E0, 0x9},
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{0x200, 0x1},
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{0x202, 0x7},
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{0xE0, 0x20},
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{0x210, 0x29},
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{0x250, 0x34},
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{0x290, 0x1},
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{0x292, 0x2},
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{0x2A1, 0x1},
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{0x2A5, 0x1},
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{0x2A8, 0x2},
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{0x2AC, 0x3},
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{0x2CA, 0x1},
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{0x2CC, 0x1},
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{0x2CE, 0x1},
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{0x300, 0x9},
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{0x30C, 0x1},
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{0x312, 0x1},
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{0x316, 0x2},
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{0x343, 0x2},
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{0x349, 0x3},
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{0x34C, 0x2},
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{0x351, 0x1},
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{0x37E, 0x6},
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{0x2B4, 0x3},
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{0x2B8, 0x3},
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{0x2BC, 0x3},
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{0x2C0, 0x3},
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{0x2C8, 0x1},
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{0x29B, 0x1},
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{0x8C, 0x1},
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{0xD5, 0x1},
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{0x284, 0xC}
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};
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GX2RegLoadPktEntry_t resourceReg_loadPktEntries[9] = // base: 0xE000
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{
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{0, 0x70}, // ps tex
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{0x380, 0x70},
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{0x460, 0x70}, // vs tex
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{0x7E0, 0x70},
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{0x8B9, 0x7},
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{0x8C0, 0x70},
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{0x930, 0x70}, // gs tex
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{0xCB0, 0x70},
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{0xD89, 0x7}
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};
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typedef struct
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{
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// Hardware view of context state (register areas)
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uint32 areaConfigReg[_GX2_CALC_SHADOWMEM_NUM_U32(GPU7_REG_AREA_SIZE_CONFIG_REG)];
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uint32 areaContextReg[_GX2_CALC_SHADOWMEM_NUM_U32(GPU7_REG_AREA_SIZE_CONTEXT_REG)];
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uint32 areaALUConst[_GX2_CALC_SHADOWMEM_NUM_U32(GPU7_REG_AREA_SIZE_ALU_CONST)];
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uint32 areaLoopConst[_GX2_CALC_SHADOWMEM_NUM_U32(GPU7_REG_AREA_SIZE_LOOP_CONST)];
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uint32 areaResource[_GX2_CALC_SHADOWMEM_NUM_U32(GPU7_REG_AREA_SIZE_RESOURCE)];
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uint32 areaSampler[_GX2_CALC_SHADOWMEM_NUM_U32(GPU7_REG_AREA_SIZE_SAMPLER)];
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}GX2HwContextState_t;
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typedef struct
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{
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GX2HwContextState_t hwContext;
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uint32 enableProfling;
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/* + 0x9804 */ uint32be loadDL_size;
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uint8 ukn9808[0x3FC-4];
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uint8 ukn9C00[0x200];
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/* +0x9E00 */ uint8 loadDL_buffer[0x300]; // this displaylist caches the IT_LOAD_* commands for swapping out context
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}GX2ContextState_t;
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static_assert(offsetof(GX2ContextState_t, loadDL_size) == 0x9804);
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static_assert(sizeof(GX2ContextState_t) == 0xA100);
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uint32 _GX2Context_CalcShadowMemSize(uint32 regCount)
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{
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return (regCount*4+0xFF)&~0xFF;
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}
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uint32 _GX2Context_CalcStateSize()
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{
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uint32 contextStateSize = 0;
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contextStateSize += _GX2Context_CalcShadowMemSize(GPU7_REG_AREA_SIZE_CONFIG_REG);
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contextStateSize += _GX2Context_CalcShadowMemSize(GPU7_REG_AREA_SIZE_CONTEXT_REG);
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contextStateSize += _GX2Context_CalcShadowMemSize(GPU7_REG_AREA_SIZE_ALU_CONST);
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contextStateSize += _GX2Context_CalcShadowMemSize(GPU7_REG_AREA_SIZE_LOOP_CONST);
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contextStateSize += _GX2Context_CalcShadowMemSize(GPU7_REG_AREA_SIZE_RESOURCE);
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contextStateSize += _GX2Context_CalcShadowMemSize(GPU7_REG_AREA_SIZE_SAMPLER);
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return contextStateSize;
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}
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void _GX2Context_CreateLoadDL()
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{
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GX2::GX2ReserveCmdSpace(3);
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_CONTEXT_CONTROL, 2));
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gx2WriteGather_submitU32AsBE(0x80000077);
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gx2WriteGather_submitU32AsBE(0x80000077);
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}
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void _GX2Context_WriteCmdDisableStateShadowing()
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{
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GX2::GX2ReserveCmdSpace(3);
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_CONTEXT_CONTROL, 2));
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gx2WriteGather_submitU32AsBE(0x80000000);
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gx2WriteGather_submitU32AsBE(0x80000000);
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}
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void _GX2Context_cmdLoad(void* gx2ukn, uint32 pm4Header, MPTR physAddrRegArea, uint32 waitForIdle, uint32 numRegOffsetEntries, GX2RegLoadPktEntry_t* regOffsetEntries)
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{
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GX2::GX2ReserveCmdSpace(3 + numRegOffsetEntries*2);
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gx2WriteGather_submitU32AsBE(pm4Header);
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gx2WriteGather_submitU32AsBE(physAddrRegArea);
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gx2WriteGather_submitU32AsBE(waitForIdle);
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for(uint32 i=0; i<numRegOffsetEntries; i++)
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{
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gx2WriteGather_submitU32AsBE(regOffsetEntries[i].regOffset); // regOffset
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gx2WriteGather_submitU32AsBE(regOffsetEntries[i].regCount); // regCount
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}
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}
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#define __cmdStateLoad(__gx2State, __pm4Command, __regArea, __waitForIdle, __regLoadPktEntries) _GX2Context_cmdLoad(NULL, pm4HeaderType3(__pm4Command, 2+sizeof(__regLoadPktEntries)/sizeof(__regLoadPktEntries[0])*2), memory_virtualToPhysical(memory_getVirtualOffsetFromPointer(__regArea)), __waitForIdle, sizeof(__regLoadPktEntries)/sizeof(__regLoadPktEntries[0]), __regLoadPktEntries)
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void _GX2Context_WriteCmdRestoreState(GX2ContextState_t* gx2ContextState, uint32 ukn)
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{
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MPTR physAddrContextState = memory_virtualToPhysical(memory_getVirtualOffsetFromPointer(gx2ContextState));
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_GX2Context_CreateLoadDL();
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__cmdStateLoad(NULL, IT_LOAD_CONFIG_REG, gx2ContextState->hwContext.areaConfigReg, 0x80000000, configReg_loadPktEntries);
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__cmdStateLoad(NULL, IT_LOAD_CONTEXT_REG, gx2ContextState->hwContext.areaContextReg, 0, contextReg_loadPktEntries);
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__cmdStateLoad(NULL, IT_LOAD_ALU_CONST, gx2ContextState->hwContext.areaALUConst, 0, aluConst_loadPktEntries);
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__cmdStateLoad(NULL, IT_LOAD_LOOP_CONST, gx2ContextState->hwContext.areaLoopConst, 0, loopConst_loadPktEntries);
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__cmdStateLoad(NULL, IT_LOAD_RESOURCE, gx2ContextState->hwContext.areaResource, 0, resourceReg_loadPktEntries);
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__cmdStateLoad(NULL, IT_LOAD_SAMPLER, gx2ContextState->hwContext.areaSampler, 0, samplerReg_loadPktEntries);
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}
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void GX2SetDefaultState()
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{
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GX2::GX2ReserveCmdSpace(0x100);
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Latte::LATTE_PA_CL_VTE_CNTL reg{};
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reg.set_VPORT_X_OFFSET_ENA(true).set_VPORT_X_SCALE_ENA(true);
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reg.set_VPORT_Y_OFFSET_ENA(true).set_VPORT_Y_SCALE_ENA(true);
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reg.set_VPORT_Z_OFFSET_ENA(true).set_VPORT_Z_SCALE_ENA(true);
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reg.set_VTX_W0_FMT(true);
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gx2WriteGather_submit(pm4HeaderType3(IT_SET_CONTEXT_REG, 1 + 1),
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Latte::REGADDR::PA_CL_VTE_CNTL - 0xA000,
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reg);
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uint32 stencilTestEnable = GX2_FALSE;
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uint32 backStencilEnable = GX2_FALSE;
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uint32 frontStencilFunc = 0;
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uint32 frontStencilZPass = 0;
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uint32 frontStencilZFail = 0;
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uint32 frontStencilFail = 0;
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uint32 backStencilFunc = 0;
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uint32 backStencilZPass = 0;
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uint32 backStencilZFail = 0;
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uint32 backStencilFail = 0;
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uint32 depthControlReg = 0;
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// depth stuff
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depthControlReg |= (1<<1);
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depthControlReg |= (1<<2);
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depthControlReg |= ((1&7)<<4);
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// stencil stuff
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depthControlReg |= ((stencilTestEnable&1)<<0);
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depthControlReg |= ((backStencilEnable&1)<<7);
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depthControlReg |= ((frontStencilFunc&7)<<8);
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depthControlReg |= ((frontStencilZPass&7)<<14);
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depthControlReg |= ((frontStencilZFail&7)<<17);
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depthControlReg |= ((frontStencilFail&7)<<11);
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depthControlReg |= ((backStencilFunc&7)<<20);
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depthControlReg |= ((backStencilZPass&7)<<26);
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depthControlReg |= ((backStencilZFail&3)<<29);
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depthControlReg |= ((backStencilFail&7)<<23);
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_SET_CONTEXT_REG, 1+1));
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gx2WriteGather_submitU32AsBE(Latte::REGADDR::DB_DEPTH_CONTROL-0xA000);
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gx2WriteGather_submitU32AsBE(depthControlReg);
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GX2::GX2SetAlphaTest(GX2_DISABLE, GX2::GX2_ALPHAFUNC::LESS, 0.0f);
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GX2::GX2SetPolygonControl(Latte::LATTE_PA_SU_SC_MODE_CNTL::E_FRONTFACE::CCW, GX2_DISABLE, GX2_DISABLE, Latte::LATTE_PA_SU_SC_MODE_CNTL::E_POLYGONMODE::UKN0, Latte::LATTE_PA_SU_SC_MODE_CNTL::E_PTYPE::TRIANGLES, Latte::LATTE_PA_SU_SC_MODE_CNTL::E_PTYPE::TRIANGLES, GX2_DISABLE, GX2_DISABLE, GX2_DISABLE);
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GX2::GX2SetPolygonOffset(0.0f, 0.0f, 0.0f, 0.0f, 0.0f);
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GX2::GX2SetPrimitiveRestartIndex(0xffffffff);
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GX2::GX2SetTargetChannelMasks(0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF);
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GX2::GX2SetBlendConstantColor(0.0f, 0.0f, 0.0f, 0.0f);
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GX2::GX2SetPointSize(1.0f, 1.0f);
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GX2::GX2SetPointLimits(1.0f, 1.0f);
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GX2::GX2SetColorControl(GX2::GX2_LOGICOP::COPY, GX2_DISABLE, GX2_DISABLE, GX2_ENABLE);
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GX2::GX2SetRasterizerClipControlEx(true, true, false);
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// Set clear depth to 1.0 (workaround for Darksiders 2. Investigate whether actual GX2 driver also sets this)
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float depth = 1.0;
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_SET_CONTEXT_REG, 1+1));
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gx2WriteGather_submitU32AsBE(mmDB_DEPTH_CLEAR - 0xA000);
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gx2WriteGather_submitU32AsBE(*(uint32*)&depth); // depth (as float)
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// reset HLE special states
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for (sint32 i = 0; i <= GX2_SPECIAL_STATE_COUNT; i++)
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{
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gx2WriteGather_submitU32AsBE(pm4HeaderType3(IT_HLE_SPECIAL_STATE, 2));
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gx2WriteGather_submitU32AsBE(i); // state id
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gx2WriteGather_submitU32AsBE(0); // disable
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}
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}
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void gx2Export_GX2SetDefaultState(PPCInterpreter_t* hCPU)
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{
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cemuLog_log(LogType::GX2, "GX2SetDefaultState()");
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GX2SetDefaultState();
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osLib_returnFromFunction(hCPU, 0);
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}
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void _GX2ContextCreateRestoreStateDL(GX2ContextState_t* gx2ContextState)
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{
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// begin display list
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cemu_assert_debug(!GX2::GX2GetDisplayListWriteStatus()); // must not already be writing to a display list
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GX2::GX2BeginDisplayList((void*)gx2ContextState->loadDL_buffer, sizeof(gx2ContextState->loadDL_buffer));
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_GX2Context_WriteCmdRestoreState(gx2ContextState, 0);
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uint32 displayListSize = GX2::GX2EndDisplayList((void*)gx2ContextState->loadDL_buffer);
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gx2ContextState->loadDL_size = displayListSize;
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}
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void gx2Export_GX2SetupContextStateEx(PPCInterpreter_t* hCPU)
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{
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cemuLog_log(LogType::GX2, "GX2SetupContextStateEx(0x{:08x})", hCPU->gpr[3]);
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cemu_assert_debug(hCPU->gpr[4] == 0 || hCPU->gpr[4] == 1);
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GX2ContextState_t* gx2ContextState = (GX2ContextState_t*)memory_getPointerFromVirtualOffset(hCPU->gpr[3]);
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uint32 hwContextSize = _GX2Context_CalcStateSize();
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if( hwContextSize != sizeof(GX2HwContextState_t) )
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assert_dbg();
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if( sizeof(GX2HwContextState_t) != 0x9800 )
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assert_dbg(); // GX2 HW context size mismatch
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if( sizeof(GX2ContextState_t) != 0xA100 )
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assert_dbg(); // GX2 context size mismatch
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memset(gx2ContextState, 0x00, sizeof(GX2ContextState_t));
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gx2ContextState->enableProfling = _swapEndianU32(hCPU->gpr[4]&1);
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_GX2Context_WriteCmdRestoreState(gx2ContextState, 1);
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gx2CurrentContextStateMPTR = hCPU->gpr[3];
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_GX2Context_CreateLoadDL();
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GX2SetDefaultState();
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_GX2ContextCreateRestoreStateDL(gx2ContextState);
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osLib_returnFromFunction(hCPU, 0);
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}
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void gx2Export_GX2SetContextState(PPCInterpreter_t* hCPU)
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{
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cemuLog_log(LogType::GX2, "GX2SetContextState(0x{:08x})", hCPU->gpr[3]);
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// parameters:
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if( hCPU->gpr[3] == MPTR_NULL )
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{
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// disable state shadowing
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_GX2Context_WriteCmdDisableStateShadowing();
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osLib_returnFromFunction(hCPU, 0);
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return;
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}
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// check if context state changed
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bool boiWorkaround = CafeSystem::GetRPXHashBase() == 0x6BCD618E; // workaround for a bug in Binding of Isaac to avoid flicker
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if( boiWorkaround )
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{
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if( hCPU->gpr[3] != gx2CurrentContextStateMPTR ) // dont reload same state
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{
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GX2ContextState_t* gx2ContextState = (GX2ContextState_t*)memory_getPointerFromVirtualOffset(hCPU->gpr[3]);
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_GX2Context_WriteCmdRestoreState(gx2ContextState, 0);
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_GX2Context_CreateLoadDL();
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// set new context state
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gx2CurrentContextStateMPTR = hCPU->gpr[3];
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}
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else
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{
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// even if it's the same context, make sure state shadowing is enabled.
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_GX2Context_CreateLoadDL();
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}
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}
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else
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{
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GX2ContextState_t* gx2ContextState = (GX2ContextState_t*)memory_getPointerFromVirtualOffset(hCPU->gpr[3]);
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if (gx2ContextState->loadDL_size == 0)
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{
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_GX2Context_CreateLoadDL();
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_GX2Context_WriteCmdRestoreState(gx2ContextState, 0);
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}
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else
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{
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_GX2Context_CreateLoadDL();
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GX2::GX2CallDisplayList(memory_getVirtualOffsetFromPointer(gx2ContextState->loadDL_buffer), gx2ContextState->loadDL_size);
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}
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// set new context state
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gx2CurrentContextStateMPTR = hCPU->gpr[3];
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}
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// todo: Save/restore GX2 special state as well -> handle this by correctly emulating the state
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osLib_returnFromFunction(hCPU, 0);
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}
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void gx2Export_GX2GetContextStateDisplayList(PPCInterpreter_t* hCPU)
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{
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cemuLog_log(LogType::GX2, "GX2GetContextStateDisplayList(0x{:08x}, 0x{:08x}, 0x{:08x})", hCPU->gpr[3], hCPU->gpr[4], hCPU->gpr[5]);
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ppcDefineParamStructPtr(gx2ContextState, GX2ContextState_t, 0);
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ppcDefineParamU32BEPtr(displayListPtrOut, 1);
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ppcDefineParamU32BEPtr(displayListSizeOut, 2);
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*displayListPtrOut = memory_getVirtualOffsetFromPointer(gx2ContextState->loadDL_buffer);
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*displayListSizeOut = gx2ContextState->loadDL_size;
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osLib_returnFromFunction(hCPU, 0);
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}
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