Ryujinx/ARMeilleure/Instructions
LDj3SNuD e36e97c64d
CPU: This PR fixes Fpscr, among other things. (#1433)
* CPU: This PR fixes Fpscr, among other things.

* Add Fpscr.Qc = 1 if sat. for Vqrshrn & Vqrshrun.

* Fix Vcmp & Vcmpe opcode table.

* Revert "Fix Vcmp & Vcmpe opcode table."

This reverts commit c117d9410d693185ff5f8ee8e457ffbfb2027dd5.

* Address PR feedbacks.
2020-08-08 17:18:51 +02:00
..
CryptoHelper.cs
InstEmitAlu32.cs
InstEmitAlu.cs Add most of the A32 instruction set to ARMeilleure (#897) 2020-02-24 08:20:40 +11:00
InstEmitAluHelper.cs
InstEmitBfm.cs
InstEmitCcmp.cs
InstEmitCsel.cs
InstEmitDiv.cs Add a new JIT compiler for CPU code (#693) 2019-08-08 21:56:22 +03:00
InstEmitException32.cs
InstEmitException.cs
InstEmitFlow32.cs
InstEmitFlow.cs
InstEmitFlowHelper.cs
InstEmitHash32.cs
InstEmitHash.cs
InstEmitHashHelper.cs
InstEmitHelper.cs
InstEmitMemory32.cs
InstEmitMemory.cs
InstEmitMemoryEx32.cs
InstEmitMemoryEx.cs
InstEmitMemoryExHelper.cs
InstEmitMemoryHelper.cs
InstEmitMove.cs
InstEmitMul32.cs
InstEmitMul.cs
InstEmitSimdArithmetic32.cs
InstEmitSimdArithmetic.cs
InstEmitSimdCmp32.cs
InstEmitSimdCmp.cs
InstEmitSimdCrypto32.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
InstEmitSimdCrypto.cs
InstEmitSimdCvt32.cs Add Profiled Persistent Translation Cache. (#769) 2020-06-16 20:28:02 +02:00
InstEmitSimdCvt.cs
InstEmitSimdHash.cs
InstEmitSimdHelper32.cs
InstEmitSimdHelper.cs
InstEmitSimdLogical32.cs
InstEmitSimdLogical.cs
InstEmitSimdMemory32.cs
InstEmitSimdMemory.cs
InstEmitSimdMove32.cs Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303) 2020-06-24 10:43:44 +10:00
InstEmitSimdMove.cs
InstEmitSimdShift32.cs
InstEmitSimdShift.cs
InstEmitSystem32.cs
InstEmitSystem.cs
InstName.cs
NativeInterface.cs
SoftFallback.cs
SoftFloat.cs