gdkchan ab9d4b862d Implement VORN (register) Arm32 instruction (#2396)		2021-06-23 23:21:23 +02:00
..
CryptoHelper.cs
InstEmitAlu32.cs	Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)	2020-12-17 20:43:41 +01:00
InstEmitAlu.cs
InstEmitAluHelper.cs	Clear JIT cache on exit (#1518)	2020-12-16 17:07:42 -03:00
InstEmitBfm.cs
InstEmitCcmp.cs
InstEmitCsel.cs
InstEmitDiv.cs
InstEmitException32.cs
InstEmitException.cs
InstEmitFlow32.cs
InstEmitFlow.cs
InstEmitFlowHelper.cs	Add multi-level function table (#2228)	2021-05-29 18:06:28 -03:00
InstEmitHash32.cs
InstEmitHash.cs
InstEmitHashHelper.cs
InstEmitHelper.cs	Clear JIT cache on exit (#1518)	2020-12-16 17:07:42 -03:00
InstEmitMemory32.cs
InstEmitMemory.cs	Fold constant offsets and group constant addresses (#2285)	2021-05-13 21:26:57 +02:00
InstEmitMemoryEx32.cs
InstEmitMemoryEx.cs	Implement PRFM (register variant) as NOP (#1956)	2021-01-26 16:09:27 +11:00
InstEmitMemoryExHelper.cs	Validate CPU virtual addresses on access (#1987)	2021-02-16 19:04:19 +01:00
InstEmitMemoryHelper.cs	Add multi-level function table (#2228)	2021-05-29 18:06:28 -03:00
InstEmitMove.cs
InstEmitMul32.cs	Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)	2020-12-17 20:43:41 +01:00
InstEmitMul.cs
InstEmitSimdArithmetic32.cs	Implement VCNT instruction (#1963)	2021-02-22 16:26:13 +01:00
InstEmitSimdArithmetic.cs	Improve accuracy of reciprocal step instructions (#2305)	2021-05-24 20:20:07 +10:00
InstEmitSimdCmp32.cs
InstEmitSimdCmp.cs
InstEmitSimdCrypto32.cs
InstEmitSimdCrypto.cs
InstEmitSimdCvt32.cs	CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)	2020-12-16 20:27:15 -03:00
InstEmitSimdCvt.cs
InstEmitSimdHash.cs
InstEmitSimdHelper32.cs	CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)	2021-01-04 23:45:54 +01:00
InstEmitSimdHelper.cs	Add BIC/ORR Vd.T, #imm fast path (#2279)	2021-05-20 09:09:17 -03:00
InstEmitSimdLogical32.cs	Implement VORN (register) Arm32 instruction (#2396)	2021-06-23 23:21:23 +02:00
InstEmitSimdLogical.cs	Add BIC/ORR Vd.T, #imm fast path (#2279)	2021-05-20 09:09:17 -03:00
InstEmitSimdMemory32.cs
InstEmitSimdMemory.cs
InstEmitSimdMove32.cs
InstEmitSimdMove.cs
InstEmitSimdShift32.cs
InstEmitSimdShift.cs
InstEmitSystem32.cs
InstEmitSystem.cs
InstName.cs	Implement VORN (register) Arm32 instruction (#2396)	2021-06-23 23:21:23 +02:00
NativeInterface.cs	Add multi-level function table (#2228)	2021-05-29 18:06:28 -03:00
SoftFallback.cs	Implement VCNT instruction (#1963)	2021-02-22 16:26:13 +01:00
SoftFloat.cs