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Merge 7ef7146502 into a71d3b8cab
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9beb4b01cd
@ -1053,6 +1053,14 @@ const char * fallback_cpu_detection()
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return s_result.c_str();
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#else
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// Prefer a concrete host -mcpu (e.g. apple-m2) so LLVM uses the right scheduling model.
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// MIDR_EL1 is exposed via sysfs on Linux; see aarch64::get_cpu_llvm_name().
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static const std::string s_mcpu = aarch64::get_cpu_llvm_name();
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if (!s_mcpu.empty())
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{
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return s_mcpu.c_str();
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}
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// TODO: Read the data from /proc/cpuinfo. ARM CPU registers are not accessible from usermode.
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// This will be a pain when supporting snapdragon on windows but we'll cross that bridge when we get there.
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// Require at least armv8-2a. Older chips are going to be useless anyway.
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@ -83,6 +83,8 @@ namespace aarch64
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{ 0x61, 0x25, "armv8.5-a", "M1 Pro", "Icestorm" },
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{ 0x61, 0x32, "armv8.5-a", "M2", "Avalanche" },
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{ 0x61, 0x33, "armv8.5-a", "M2", "Blizzard" },
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{ 0x61, 0x38, "armv8.5-a+fp16+bf16+i8mm+dotprod", "M2 Pro/Max", "Avalanche" },
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{ 0x61, 0x39, "armv8.5-a+fp16+bf16+i8mm+dotprod", "M2 Pro/Max", "Blizzard" },
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// QUALCOMM
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{ 0x51, 0x01, "armv8.5-a", "Snapdragon", "X-Elite" },
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@ -136,7 +138,9 @@ namespace aarch64
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#endif
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}
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std::string get_cpu_name()
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// Resolve the representative CPU part entry for this machine (the "lowest" core in a
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// big.LITTLE layout), or nullptr if the layout can't be fully identified.
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static const cpu_entry_t* get_cpu_part_info()
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{
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std::map<u64, int> core_layout;
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for (u32 i = 0; i < std::thread::hardware_concurrency(); ++i)
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@ -152,10 +156,10 @@ namespace aarch64
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if (core_layout.empty())
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{
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return {};
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return nullptr;
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}
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const cpu_entry_t* lowest_part_info = nullptr;
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const cpu_entry_t* lowest_part_info = nullptr;
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for (const auto& [midr, count] : core_layout)
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{
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const auto implementer_id = (midr >> 24) & 0xff;
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@ -164,7 +168,7 @@ namespace aarch64
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const auto part_info = find_cpu_part(implementer_id, part_id);
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if (!part_info)
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{
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return {};
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return nullptr;
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}
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if (lowest_part_info == nullptr || lowest_part_info > part_info)
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@ -173,7 +177,13 @@ namespace aarch64
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}
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}
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return lowest_part_info ? lowest_part_info->name : "";
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return lowest_part_info;
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}
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std::string get_cpu_name()
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{
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const auto part_info = get_cpu_part_info();
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return part_info ? part_info->name : "";
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}
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std::string get_cpu_brand()
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@ -239,6 +249,27 @@ namespace aarch64
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result += suffix;
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return result;
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}
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std::string get_cpu_llvm_name()
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{
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const auto part_info = get_cpu_part_info();
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// Only Apple silicon (implementer 0x61) gets a hand-picked -mcpu for now. The family
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// field holds the SoC generation ("M2", "M2 Pro/Max", ...) whose first token maps
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// directly onto the LLVM "apple-mN" targets (and auto-extends to future generations).
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if (!part_info || part_info->vendor != 0x61 || !part_info->family || !part_info->family[0])
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{
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return {};
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}
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const auto tokens = fmt::split_sv(part_info->family, {" "});
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if (tokens.empty())
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{
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return {};
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}
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return fmt::format("apple-%s", fmt::to_lower(tokens.front()));
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}
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#else
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static std::string sysctl_s(const std::string_view& variable_name)
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{
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@ -297,5 +328,28 @@ namespace aarch64
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return fmt::format("%s (%lluP+%lluE)", brand, pcores, ecores);
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}
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std::string get_cpu_llvm_name()
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{
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// machdep.cpu.brand_string on Apple silicon is "Apple <family>", e.g. "Apple M2 Max",
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// "Apple M1 Pro", "Apple M4". The generation token after the "Apple " vendor prefix maps
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// directly onto the LLVM "apple-mN"/"apple-aN" targets.
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const auto brand = sysctl_s("machdep.cpu.brand_string");
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std::string_view family = brand;
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if (!family.starts_with("Apple "))
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{
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return {};
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}
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family.remove_prefix(6);
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const auto tokens = fmt::split_sv(family, {" "});
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if (tokens.empty())
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{
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return {};
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}
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return fmt::format("apple-%s", fmt::to_lower(tokens.front()));
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}
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#endif
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}
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@ -39,4 +39,8 @@ namespace aarch64
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std::string get_cpu_name();
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std::string get_cpu_brand();
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// Returns a concrete LLVM -mcpu name for the host (e.g. "apple-m2") or "" if unknown.
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// Used to give the JIT the correct scheduling model instead of a generic fallback.
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std::string get_cpu_llvm_name();
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}
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