mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2026-04-29 23:41:19 -06:00
VOP decoding for Neo (#4301)
This commit is contained in:
Marcin Mikołajczyk
GitHub
parent
c68a8baa94
commit
07a0475d0f
@ -239,11 +239,11 @@ uint32_t GcnDecodeContext::mapEncodingOp(InstEncoding encoding, Opcode opcode) {
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uint32_t op =
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static_cast<uint32_t>(opcode) - static_cast<uint32_t>(OpcodeMap::OP_MAP_VOPC);
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encodingOp = op + static_cast<uint32_t>(OpMapVOP3VOPX::VOP3_TO_VOPC);
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} else if (opcode >= Opcode::V_CNDMASK_B32 && opcode <= Opcode::V_CVT_PK_I16_I32) {
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} else if (opcode >= Opcode::V_CNDMASK_B32 && opcode <= Opcode::V_LDEXP_F16) {
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uint32_t op =
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static_cast<uint32_t>(opcode) - static_cast<uint32_t>(OpcodeMap::OP_MAP_VOP2);
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encodingOp = op + static_cast<uint32_t>(OpMapVOP3VOPX::VOP3_TO_VOP2);
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} else if (opcode >= Opcode::V_NOP && opcode <= Opcode::V_MOVRELSD_B32) {
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} else if (opcode >= Opcode::V_NOP && opcode <= Opcode::V_SQRT_F16) {
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uint32_t op =
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static_cast<uint32_t>(opcode) - static_cast<uint32_t>(OpcodeMap::OP_MAP_VOP1);
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encodingOp = op + static_cast<uint32_t>(OpMapVOP3VOPX::VOP3_TO_VOP1);
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@ -440,6 +440,30 @@ void GcnDecodeContext::decodeSubDwordAddressing(InstEncoding encoding, GcnCodeSl
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if (encoding == InstEncoding::VOPC) {
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SdwaVopc sdwa = *reinterpret_cast<SdwaVopc*>(&m_instruction.src[0].code);
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m_instruction.src[0].field =
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sdwa.s0 == 0 ? OperandField::VectorGPR : getOperandField(sdwa.src0);
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m_instruction.src[0].code = sdwa.src0;
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m_instruction.src[0].sdwa_sel = SdwaSelector(sdwa.src0_sel);
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m_instruction.src[0].input_modifier.neg = sdwa.src0_neg;
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m_instruction.src[0].input_modifier.abs = sdwa.src0_abs;
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m_instruction.src[0].input_modifier.sext = sdwa.src0_sext;
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m_instruction.src[1].field =
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sdwa.s1 == 0 ? OperandField::VectorGPR : getOperandField(m_instruction.src[1].code);
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m_instruction.src[1].sdwa_sel = SdwaSelector(sdwa.src1_sel);
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m_instruction.src[1].input_modifier.neg = sdwa.src1_neg;
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m_instruction.src[1].input_modifier.abs = sdwa.src1_abs;
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m_instruction.src[1].input_modifier.sext = sdwa.src1_sext;
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m_instruction.dst[0].field = sdwa.sd ? OperandField::ScalarGPR : OperandField::VccLo;
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m_instruction.dst[0].code = sdwa.sdst;
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} else if (encoding == InstEncoding::VOP1 || encoding == InstEncoding::VOP2) {
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SdwaVop12 sdwa = *reinterpret_cast<SdwaVop12*>(&m_instruction.src[0].code);
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m_instruction.src[0].field =
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sdwa.s0 == 0 ? OperandField::VectorGPR : getOperandField(sdwa.src0);
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m_instruction.src[0].code = sdwa.src0;
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@ -475,27 +499,6 @@ void GcnDecodeContext::decodeSubDwordAddressing(InstEncoding encoding, GcnCodeSl
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m_instruction.dst[0].output_modifier.multiplier = 0.5f;
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break;
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}
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} else if (encoding == InstEncoding::VOP1 || encoding == InstEncoding::VOP2) {
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SdwaVop12 sdwa = *reinterpret_cast<SdwaVop12*>(&m_instruction.src[0].code);
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m_instruction.src[0].field =
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sdwa.s0 == 0 ? OperandField::VectorGPR : getOperandField(sdwa.src0);
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m_instruction.src[0].code = sdwa.src0;
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m_instruction.src[0].sdwa_sel = SdwaSelector(sdwa.src0_sel);
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m_instruction.src[0].input_modifier.neg = sdwa.src0_neg;
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m_instruction.src[0].input_modifier.abs = sdwa.src0_abs;
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m_instruction.src[0].input_modifier.sext = sdwa.src0_sext;
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m_instruction.src[1].field =
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sdwa.s1 == 0 ? OperandField::VectorGPR : getOperandField(m_instruction.src[1].code);
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m_instruction.src[1].sdwa_sel = SdwaSelector(sdwa.src1_sel);
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m_instruction.src[1].input_modifier.neg = sdwa.src1_neg;
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m_instruction.src[1].input_modifier.abs = sdwa.src1_abs;
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m_instruction.src[1].input_modifier.sext = sdwa.src1_sext;
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m_instruction.dst[0].field = sdwa.sd ? OperandField::ScalarGPR : OperandField::VccLo;
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m_instruction.dst[0].code = sdwa.sdst;
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} else {
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LOG_WARNING(Render_Recompiler, "illegal instruction: SDWA used outside VOP1/VOP2/VOPC");
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}
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@ -692,6 +695,8 @@ void GcnDecodeContext::decodeInstructionVOP3(uint64_t hexInstruction) {
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u32 vdst = bit::extract(hexInstruction, 7, 0);
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u32 sdst = bit::extract(hexInstruction, 14, 8); // For VOP3B
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u32 op = bit::extract(hexInstruction, 25, 17);
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u32 op_msb = bit::extract(hexInstruction, 16, 16);
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op = op + op_msb * (1 << 9);
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u32 src0 = bit::extract(hexInstruction, 40, 32);
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u32 src1 = bit::extract(hexInstruction, 49, 41);
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u32 src2 = bit::extract(hexInstruction, 58, 50);
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@ -703,13 +708,13 @@ void GcnDecodeContext::decodeInstructionVOP3(uint64_t hexInstruction) {
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m_instruction.opcode =
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static_cast<Opcode>(vopcOp + static_cast<u32>(OpcodeMap::OP_MAP_VOPC));
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} else if (op >= static_cast<u32>(OpcodeVOP3::V_CNDMASK_B32) &&
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op <= static_cast<u32>(OpcodeVOP3::V_CVT_PK_I16_I32)) {
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op <= static_cast<u32>(OpcodeVOP3::V_LDEXP_F16)) {
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// Map from VOP3 to VOP2
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u32 vop2Op = op - static_cast<u32>(OpMapVOP3VOPX::VOP3_TO_VOP2);
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m_instruction.opcode =
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static_cast<Opcode>(vop2Op + static_cast<u32>(OpcodeMap::OP_MAP_VOP2));
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} else if (op >= static_cast<u32>(OpcodeVOP3::V_NOP) &&
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op <= static_cast<u32>(OpcodeVOP3::V_MOVRELSD_B32)) {
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op <= static_cast<u32>(OpcodeVOP3::V_SQRT_F16)) {
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// Map from VOP3 to VOP1
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u32 vop1Op = op - static_cast<u32>(OpMapVOP3VOPX::VOP3_TO_VOP1);
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m_instruction.opcode =
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@ -769,8 +774,14 @@ void GcnDecodeContext::decodeInstructionVOP3(uint64_t hexInstruction) {
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if (control.neg & (1u << i)) {
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m_instruction.src[i].input_modifier.neg = true;
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}
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if (control.op_sel & (1u << i)) {
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m_instruction.src[i].op_sel.op_sel = true;
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}
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}
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m_instruction.dst[0].op_sel.op_sel = control.op_sel & (1u << 3);
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// update output modifier
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auto& outputMod = m_instruction.dst[0].output_modifier;
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@ -115,7 +115,8 @@ struct InstControlVOP3 {
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u64 : 8;
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u64 abs : 3;
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u64 clmp : 1;
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u64 : 47;
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u64 op_sel : 4;
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u64 : 43;
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u64 omod : 2;
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u64 neg : 3;
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};
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@ -130,7 +131,7 @@ struct InstControlVOP3P {
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u64 op_sel_hi_01 : 2;
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u64 neg : 3;
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bool get_op_sel_hi(int idx) {
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bool get_op_sel_hi(int idx) const {
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switch (idx) {
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case 0:
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return (op_sel_hi_01 & 1) == 1;
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@ -240,7 +241,7 @@ union InstControl {
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InstControlEXP exp;
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};
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struct SdwaVopc {
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struct SdwaVop12 {
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u32 src0 : 8;
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u32 dst_sel : 3;
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u32 dst_u : 2;
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@ -261,7 +262,7 @@ struct SdwaVopc {
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u32 s1 : 1;
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};
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struct SdwaVop12 {
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struct SdwaVopc {
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u32 src0 : 8;
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u32 sdst : 7;
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u32 sd : 1;
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@ -259,8 +259,15 @@ enum class OpcodeVOP2 : u32 {
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V_CVT_PKRTZ_F16_F32 = 47,
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V_CVT_PK_U16_U32 = 48,
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V_CVT_PK_I16_I32 = 49,
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V_ADD_F16 = 50,
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V_SUB_F16 = 51,
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V_SUBREV_F16 = 52,
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V_MUL_F16 = 53,
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V_MAX_F16 = 57,
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V_MIN_F16 = 58,
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V_LDEXP_F16 = 59,
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OP_RANGE_VOP2 = V_CVT_PK_I16_I32 + 1,
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OP_RANGE_VOP2 = V_LDEXP_F16 + 1,
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};
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enum class OpcodeVOP3 : u32 {
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@ -411,6 +418,12 @@ enum class OpcodeVOP3 : u32 {
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V_CMP_TRU_I32 = 135,
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V_CMP_T_I32 = 135,
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V_CMP_CLASS_F32 = 136,
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V_CMP_LT_I16 = 137,
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V_CMP_EQ_I16 = 138,
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V_CMP_LE_I16 = 139,
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V_CMP_GT_I16 = 140,
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V_CMP_NE_I16 = 141,
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V_CMP_GE_I16 = 142,
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V_CMPX_F_I32 = 144,
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V_CMPX_LT_I32 = 145,
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V_CMPX_EQ_I32 = 146,
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@ -433,6 +446,12 @@ enum class OpcodeVOP3 : u32 {
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V_CMP_TRU_I64 = 167,
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V_CMP_T_I64 = 167,
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V_CMP_CLASS_F64 = 168,
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V_CMP_LT_U16 = 169,
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V_CMP_EQ_U16 = 170,
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V_CMP_LE_U16 = 171,
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V_CMP_GT_U16 = 172,
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V_CMP_NE_U16 = 173,
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V_CMP_GE_U16 = 174,
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V_CMPX_F_I64 = 176,
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V_CMPX_LT_I64 = 177,
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V_CMPX_EQ_I64 = 178,
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@ -454,6 +473,14 @@ enum class OpcodeVOP3 : u32 {
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V_CMP_GE_U32 = 198,
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V_CMP_TRU_U32 = 199,
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V_CMP_T_U32 = 199,
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V_CMP_F_F16 = 200,
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V_CMP_LT_F16 = 201,
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V_CMP_EQ_F16 = 202,
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V_CMP_LE_F16 = 203,
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V_CMP_GT_F16 = 204,
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V_CMP_LG_F16 = 205,
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V_CMP_GE_F16 = 206,
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V_CMP_O_F16 = 207,
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V_CMPX_F_U32 = 208,
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V_CMPX_LT_U32 = 209,
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V_CMPX_EQ_U32 = 210,
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@ -534,6 +561,13 @@ enum class OpcodeVOP3 : u32 {
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V_CVT_PKRTZ_F16_F32 = 303,
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V_CVT_PK_U16_U32 = 304,
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V_CVT_PK_I16_I32 = 305,
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V_ADD_F16 = 306,
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V_SUB_F16 = 307,
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V_SUBREV_F16 = 308,
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V_MUL_F16 = 309,
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V_MAX_F16 = 313,
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V_MIN_F16 = 314,
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V_LDEXP_F16 = 315,
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V_MAD_LEGACY_F32 = 320,
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V_MAD_F32 = 321,
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V_MAD_I32_I24 = 322,
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@ -658,8 +692,28 @@ enum class OpcodeVOP3 : u32 {
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V_MOVRELSD_B32 = 452,
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V_LOG_LEGACY_F32 = 453,
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V_EXP_LEGACY_F32 = 454,
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V_RCP_F16 = 468,
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V_SQRT_F16 = 469,
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OP_RANGE_VOP3 = V_EXP_LEGACY_F32 + 1,
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V_ADD_NC_U16 = 771,
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V_LSHRREV_B16 = 775,
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V_ASHRREV_I16 = 776,
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V_ADD_NC_I16 = 781,
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V_SUB_NC_I16 = 782,
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V_SUB_CO_U32 = 784,
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V_LSHLREV_B16 = 788,
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V_MAD_F16 = 833,
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V_LSHL_ADD_U32 = 838,
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V_ADD_LSHL_U32 = 839,
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V_MIN3_F16 = 849,
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V_MAX3_F16 = 852,
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V_MAD_I16 = 862,
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V_ADD3_U32 = 877,
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V_LSHL_OR_B32 = 879,
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V_AND_OR_B32 = 881,
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V_OR3_B32 = 882,
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OP_RANGE_VOP3 = 1024, // in neo mode, VOP3 gets an additional bit for OP so round up
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};
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enum class OpcodeVOP3P : u32 {
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@ -756,8 +810,10 @@ enum class OpcodeVOP1 : u32 {
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V_MOVRELSD_B32 = 68,
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V_LOG_LEGACY_F32 = 69,
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V_EXP_LEGACY_F32 = 70,
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V_RCP_F16 = 84,
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V_SQRT_F16 = 85,
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OP_RANGE_VOP1 = V_EXP_LEGACY_F32 + 1,
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OP_RANGE_VOP1 = V_SQRT_F16 + 1,
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};
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enum class OpcodeVOPC : u32 {
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@ -908,6 +964,12 @@ enum class OpcodeVOPC : u32 {
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V_CMP_TRU_I32 = 135,
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V_CMP_T_I32 = 135,
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V_CMP_CLASS_F32 = 136,
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V_CMP_LT_I16 = 137,
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V_CMP_EQ_I16 = 138,
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V_CMP_LE_I16 = 139,
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V_CMP_GT_I16 = 140,
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V_CMP_NE_I16 = 141,
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V_CMP_GE_I16 = 142,
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V_CMPX_F_I32 = 144,
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V_CMPX_LT_I32 = 145,
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V_CMPX_EQ_I32 = 146,
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@ -930,6 +992,12 @@ enum class OpcodeVOPC : u32 {
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V_CMP_TRU_I64 = 167,
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V_CMP_T_I64 = 167,
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V_CMP_CLASS_F64 = 168,
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V_CMP_LT_U16 = 169,
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V_CMP_EQ_U16 = 170,
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V_CMP_LE_U16 = 171,
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V_CMP_GT_U16 = 172,
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V_CMP_NE_U16 = 173,
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V_CMP_GE_U16 = 174,
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V_CMPX_F_I64 = 176,
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V_CMPX_LT_I64 = 177,
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V_CMPX_EQ_I64 = 178,
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@ -951,6 +1019,14 @@ enum class OpcodeVOPC : u32 {
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V_CMP_GE_U32 = 198,
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V_CMP_TRU_U32 = 199,
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V_CMP_T_U32 = 199,
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V_CMP_F_F16 = 200,
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V_CMP_LT_F16 = 201,
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V_CMP_EQ_F16 = 202,
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V_CMP_LE_F16 = 203,
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V_CMP_GT_F16 = 204,
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V_CMP_LG_F16 = 205,
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V_CMP_GE_F16 = 206,
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V_CMP_O_F16 = 207,
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V_CMPX_F_U32 = 208,
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V_CMPX_LT_U32 = 209,
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V_CMPX_EQ_U32 = 210,
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@ -1653,6 +1729,12 @@ enum class Opcode : u32 {
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V_CMP_TRU_I32 = 135 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_T_I32 = 135 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_CLASS_F32 = 136 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_LT_I16 = 137 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_EQ_I16 = 138 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_LE_I16 = 139 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_GT_I16 = 140 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_NE_I16 = 141 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_GE_I16 = 142 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMPX_F_I32 = 144 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMPX_LT_I32 = 145 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMPX_EQ_I32 = 146 + (u32)OpcodeMap::OP_MAP_VOPC,
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@ -1675,6 +1757,12 @@ enum class Opcode : u32 {
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V_CMP_TRU_I64 = 167 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_T_I64 = 167 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_CLASS_F64 = 168 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_LT_U16 = 169 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_EQ_U16 = 170 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_LE_U16 = 171 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_GT_U16 = 172 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_NE_U16 = 173 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_GE_U16 = 174 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMPX_F_I64 = 176 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMPX_LT_I64 = 177 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMPX_EQ_I64 = 178 + (u32)OpcodeMap::OP_MAP_VOPC,
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@ -1695,6 +1783,14 @@ enum class Opcode : u32 {
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V_CMP_GE_U32 = 198 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_TRU_U32 = 199 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_T_U32 = 199 + (u32)OpcodeMap::OP_MAP_VOPC,
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V_CMP_F_F16 = 200 + (u32)OpcodeMap::OP_MAP_VOPC,
|
||||
V_CMP_LT_F16 = 201 + (u32)OpcodeMap::OP_MAP_VOPC,
|
||||
V_CMP_EQ_F16 = 202 + (u32)OpcodeMap::OP_MAP_VOPC,
|
||||
V_CMP_LE_F16 = 203 + (u32)OpcodeMap::OP_MAP_VOPC,
|
||||
V_CMP_GT_F16 = 204 + (u32)OpcodeMap::OP_MAP_VOPC,
|
||||
V_CMP_LG_F16 = 205 + (u32)OpcodeMap::OP_MAP_VOPC,
|
||||
V_CMP_GE_F16 = 206 + (u32)OpcodeMap::OP_MAP_VOPC,
|
||||
V_CMP_O_F16 = 207 + (u32)OpcodeMap::OP_MAP_VOPC,
|
||||
V_CMPX_F_U32 = 208 + (u32)OpcodeMap::OP_MAP_VOPC,
|
||||
V_CMPX_LT_U32 = 209 + (u32)OpcodeMap::OP_MAP_VOPC,
|
||||
V_CMPX_EQ_U32 = 210 + (u32)OpcodeMap::OP_MAP_VOPC,
|
||||
@ -1775,6 +1871,13 @@ enum class Opcode : u32 {
|
||||
V_CVT_PKRTZ_F16_F32 = 47 + (u32)OpcodeMap::OP_MAP_VOP2,
|
||||
V_CVT_PK_U16_U32 = 48 + (u32)OpcodeMap::OP_MAP_VOP2,
|
||||
V_CVT_PK_I16_I32 = 49 + (u32)OpcodeMap::OP_MAP_VOP2,
|
||||
V_ADD_F16 = 50 + (u32)OpcodeMap::OP_MAP_VOP2,
|
||||
V_SUB_F16 = 51 + (u32)OpcodeMap::OP_MAP_VOP2,
|
||||
V_SUBREV_F16 = 52 + (u32)OpcodeMap::OP_MAP_VOP2,
|
||||
V_MUL_F16 = 53 + (u32)OpcodeMap::OP_MAP_VOP2,
|
||||
V_MAX_F16 = 57 + (u32)OpcodeMap::OP_MAP_VOP2,
|
||||
V_MIN_F16 = 58 + (u32)OpcodeMap::OP_MAP_VOP2,
|
||||
V_LDEXP_F16 = 59 + (u32)OpcodeMap::OP_MAP_VOP2,
|
||||
// VOP1
|
||||
V_NOP = 0 + (u32)OpcodeMap::OP_MAP_VOP1,
|
||||
V_MOV_B32 = 1 + (u32)OpcodeMap::OP_MAP_VOP1,
|
||||
@ -1842,6 +1945,8 @@ enum class Opcode : u32 {
|
||||
V_MOVRELSD_B32 = 68 + (u32)OpcodeMap::OP_MAP_VOP1,
|
||||
V_LOG_LEGACY_F32 = 69 + (u32)OpcodeMap::OP_MAP_VOP1,
|
||||
V_EXP_LEGACY_F32 = 70 + (u32)OpcodeMap::OP_MAP_VOP1,
|
||||
V_RCP_F16 = 84 + (u32)OpcodeMap::OP_MAP_VOP1,
|
||||
V_SQRT_F16 = 85 + (u32)OpcodeMap::OP_MAP_VOP1,
|
||||
// VOP3
|
||||
V_MAD_LEGACY_F32 = 320 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_MAD_F32 = 321 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
@ -1901,6 +2006,23 @@ enum class Opcode : u32 {
|
||||
V_MQSAD_U32_U8 = 373 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_MAD_U64_U32 = 374 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_MAD_I64_I32 = 375 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_ADD_NC_U16 = 771 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_LSHRREV_B16 = 775 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_ASHRREV_I16 = 776 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_ADD_NC_I16 = 781 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_SUB_NC_I16 = 782 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_SUB_CO_U32 = 784 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_LSHLREV_B16 = 788 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_MAD_F16 = 833 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_LSHL_ADD_U32 = 838 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_ADD_LSHL_U32 = 839 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_MIN3_F16 = 849 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_MAX3_F16 = 852 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_MAD_I16 = 862 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_ADD3_U32 = 877 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_LSHL_OR_B32 = 879 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_AND_OR_B32 = 881 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
V_OR3_B32 = 882 + (u32)OpcodeMap::OP_MAP_VOP3,
|
||||
// VINTRP
|
||||
V_INTERP_P1_F32 = 0 + (u32)OpcodeMap::OP_MAP_VINTRP,
|
||||
V_INTERP_P2_F32 = 1 + (u32)OpcodeMap::OP_MAP_VINTRP,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user