From 17b38edeb505e536f2332229207d20b1565edff1 Mon Sep 17 00:00:00 2001 From: georgemoralis Date: Tue, 17 Mar 2026 07:38:32 +0200 Subject: [PATCH] avoid using u64 emmiter --- .../frontend/translate/vector_alu.cpp | 181 +++++++++--------- 1 file changed, 95 insertions(+), 86 deletions(-) diff --git a/src/shader_recompiler/frontend/translate/vector_alu.cpp b/src/shader_recompiler/frontend/translate/vector_alu.cpp index 8d8f151c2..07a3e88da 100644 --- a/src/shader_recompiler/frontend/translate/vector_alu.cpp +++ b/src/shader_recompiler/frontend/translate/vector_alu.cpp @@ -1136,108 +1136,117 @@ void Translator::V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const } void Translator::V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst) { - const IR::U64 src0 = [&]() -> IR::U64 { - switch (inst.src[0].field) { - case OperandField::ScalarGPR: { - IR::U32 low = ir.GetScalarReg(IR::ScalarReg(inst.src[0].code)); - IR::U32 high = ir.GetScalarReg(IR::ScalarReg(inst.src[0].code + 1)); - return ir.PackUint2x32(ir.CompositeConstruct(low, high)); - } - case OperandField::VectorGPR: { - IR::U32 low = ir.GetVectorReg(IR::VectorReg(inst.src[0].code)); - IR::U32 high = ir.GetVectorReg(IR::VectorReg(inst.src[0].code + 1)); - return ir.PackUint2x32(ir.CompositeConstruct(low, high)); - } - case OperandField::VccLo: { - IR::U1 vcc_bit = ir.GetVcc(); - IR::Value vcc_val = - ir.Select(vcc_bit, ir.Imm64(static_cast(-1)), ir.Imm64(static_cast(0))); - return IR::U64{vcc_val}; - } - case OperandField::ConstZero: - return ir.Imm64(static_cast(0)); - case OperandField::SignedConstIntPos: - return ir.Imm64(static_cast(inst.src[0].code)); - case OperandField::SignedConstIntNeg: { - s32 decoded_value = -s32(inst.src[0].code) + SignedConstIntNegMin - 1; - return ir.Imm64(static_cast(decoded_value)); - } - default: - UNREACHABLE_MSG("src0 = {}", u32(inst.src[0].field)); - } - }(); + ASSERT(!is_signed); - const IR::U64 src1 = [&]() -> IR::U64 { - switch (inst.src[1].field) { - case OperandField::ScalarGPR: { - IR::U32 low = ir.GetScalarReg(IR::ScalarReg(inst.src[1].code)); - IR::U32 high = ir.GetScalarReg(IR::ScalarReg(inst.src[1].code + 1)); - return ir.PackUint2x32(ir.CompositeConstruct(low, high)); - } - case OperandField::VectorGPR: { - IR::U32 low = ir.GetVectorReg(IR::VectorReg(inst.src[1].code)); - IR::U32 high = ir.GetVectorReg(IR::VectorReg(inst.src[1].code + 1)); - return ir.PackUint2x32(ir.CompositeConstruct(low, high)); - } - case OperandField::VccLo: { - IR::U1 vcc_bit = ir.GetVcc(); - IR::Value vcc_val = - ir.Select(vcc_bit, ir.Imm64(static_cast(-1)), ir.Imm64(static_cast(0))); - return IR::U64{vcc_val}; - } - case OperandField::ConstZero: - return ir.Imm64(static_cast(0)); - case OperandField::SignedConstIntPos: - return ir.Imm64(static_cast(inst.src[1].code)); - case OperandField::SignedConstIntNeg: { - s32 decoded_value = -s32(inst.src[1].code) + SignedConstIntNegMin - 1; - return ir.Imm64(static_cast(decoded_value)); - } - default: - UNREACHABLE_MSG("Unsupported src[1] operand field: {}", u32(inst.src[1].field)); - } - }(); + // Lambda to read a 64-bit operand as two 32-bit parts + auto read_u64 = [&](const InstOperand& op, bool is_src0) -> std::pair { + using enum OperandField; - // Perform the 64-bit comparison - const IR::U1 result = [&] { - switch (op) { - case ConditionOp::EQ: - return ir.IEqual(src0, src1); - case ConditionOp::LG: // NE - return ir.INotEqual(src0, src1); - case ConditionOp::GT: - return ir.IGreaterThan(src0, src1, false); // false = unsigned - case ConditionOp::LT: - return ir.ILessThan(src0, src1, false); - case ConditionOp::GE: - return ir.IGreaterThanEqual(src0, src1, false); - case ConditionOp::LE: - return ir.ILessThanEqual(src0, src1, false); - default: - UNREACHABLE_MSG("Unsupported V_CMP_U64 condition operation: {}", u32(op)); + switch (op.field) { + case ScalarGPR: + return {ir.GetScalarReg(IR::ScalarReg(op.code)), + ir.GetScalarReg(IR::ScalarReg(op.code + 1))}; + + case VectorGPR: + return {ir.GetVectorReg(IR::VectorReg(op.code)), + ir.GetVectorReg(IR::VectorReg(op.code + 1))}; + + case ConstZero: + return {ir.Imm32(0), ir.Imm32(0)}; + + case SignedConstIntPos: + return {ir.Imm32(op.code), ir.Imm32(0)}; + + case SignedConstIntNeg: { + s32 v = -s32(op.code) + SignedConstIntNegMin - 1; + return {ir.Imm32(v), ir.Imm32(v < 0 ? -1 : 0)}; } - }(); + case VccLo: + // treat as 32-bit values, zero-extend to 64-bit + { + IR::U32 val = ir.GetScalarReg(IR::ScalarReg(op.code)); + return {val, ir.Imm32(0)}; + } + default: + UNREACHABLE_MSG("Unsupported operand field {}", u32(op.field)); + } + }; + + const auto [a_lo, a_hi] = read_u64(inst.src[0], true); + const auto [b_lo, b_hi] = read_u64(inst.src[1], false); + + IR::U1 cmp_result{}; + switch (op) { + case ConditionOp::EQ: { + IR::U1 hi_eq = ir.IEqual(a_hi, b_hi); + IR::U1 lo_eq = ir.IEqual(a_lo, b_lo); + cmp_result = ir.LogicalAnd(hi_eq, lo_eq); + break; + } + + case ConditionOp::LG: { // NE + IR::U1 hi_ne = ir.INotEqual(a_hi, b_hi); + IR::U1 lo_ne = ir.INotEqual(a_lo, b_lo); + cmp_result = ir.LogicalOr(hi_ne, lo_ne); + break; + } + + case ConditionOp::GT: { + IR::U1 hi_gt = ir.IGreaterThan(a_hi, b_hi, false); + IR::U1 hi_eq = ir.IEqual(a_hi, b_hi); + IR::U1 lo_gt = ir.IGreaterThan(a_lo, b_lo, false); + cmp_result = ir.LogicalOr(hi_gt, ir.LogicalAnd(hi_eq, lo_gt)); + break; + } + + case ConditionOp::LT: { + IR::U1 hi_lt = ir.ILessThan(a_hi, b_hi, false); + IR::U1 hi_eq = ir.IEqual(a_hi, b_hi); + IR::U1 lo_lt = ir.ILessThan(a_lo, b_lo, false); + cmp_result = ir.LogicalOr(hi_lt, ir.LogicalAnd(hi_eq, lo_lt)); + break; + } + + case ConditionOp::GE: { + IR::U1 hi_gt = ir.IGreaterThan(a_hi, b_hi, false); + IR::U1 hi_eq = ir.IEqual(a_hi, b_hi); + IR::U1 lo_ge = ir.IGreaterThanEqual(a_lo, b_lo, false); + cmp_result = ir.LogicalOr(hi_gt, ir.LogicalAnd(hi_eq, lo_ge)); + break; + } + + case ConditionOp::LE: { + IR::U1 hi_lt = ir.ILessThan(a_hi, b_hi, false); + IR::U1 hi_eq = ir.IEqual(a_hi, b_hi); + IR::U1 lo_le = ir.ILessThanEqual(a_lo, b_lo, false); + cmp_result = ir.LogicalOr(hi_lt, ir.LogicalAnd(hi_eq, lo_le)); + break; + } + + default: + UNREACHABLE_MSG("Unsupported V_CMP_U64 condition {}", u32(op)); + } // Handle flags if (is_signed) { UNREACHABLE_MSG("V_CMP_U64 with signed integers is not supported"); } + if (set_exec) { UNREACHABLE_MSG("Exec setting for V_CMP_U64 is not supported"); } - // Write result (1-bit boolean) to destination switch (inst.dst[1].field) { case OperandField::VccLo: - return ir.SetVcc(result); + ir.SetVcc(cmp_result); + break; + case OperandField::ScalarGPR: - return ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[1].code), result); - case OperandField::VectorGPR: { - IR::Value result_val = ir.Select(result, ir.Imm32(1), ir.Imm32(0)); - ir.SetVectorReg(IR::VectorReg(inst.dst[1].code), IR::U32{result_val}); - } break; + ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[1].code), cmp_result); + break; + default: - UNREACHABLE_MSG("Unsupported dst field: {}", u32(inst.dst[1].field)); + UNREACHABLE_MSG("Invalid V_CMP_U64 destination"); } }