diff --git a/src/video_core/amdgpu/regs.cpp b/src/video_core/amdgpu/regs.cpp
index 17fd80312..7454eafcd 100644
--- a/src/video_core/amdgpu/regs.cpp
+++ b/src/video_core/amdgpu/regs.cpp
@@ -96,7 +96,11 @@ static_assert(GFX6_3D_REG_INDEX(vs_output_control) == 0xA207);
 static_assert(GFX6_3D_REG_INDEX(line_control) == 0xA282);
 static_assert(GFX6_3D_REG_INDEX(hs_clamp) == 0xA287);
 static_assert(GFX6_3D_REG_INDEX(vgt_gs_mode) == 0xA290);
+static_assert(GFX6_3D_REG_INDEX(vgt_gs_onchip_control) == 0xA291);
 static_assert(GFX6_3D_REG_INDEX(mode_control) == 0xA292);
+static_assert(GFX6_3D_REG_INDEX(vgt_gsvs_ring_offset_1) == 0xA298);
+static_assert(GFX6_3D_REG_INDEX(vgt_gsvs_ring_offset_2) == 0xA299);
+static_assert(GFX6_3D_REG_INDEX(vgt_gsvs_ring_offset_3) == 0xA29A);
 static_assert(GFX6_3D_REG_INDEX(vgt_gs_out_prim_type) == 0xA29B);
 static_assert(GFX6_3D_REG_INDEX(index_size) == 0xA29D);
 static_assert(GFX6_3D_REG_INDEX(index_buffer_type) == 0xA29F);
@@ -119,6 +123,8 @@ static_assert(GFX6_3D_REG_INDEX(color_buffers[0].pitch) == 0xA319);
 static_assert(GFX6_3D_REG_INDEX(color_buffers[0].slice) == 0xA31A);
 static_assert(GFX6_3D_REG_INDEX(color_buffers[7].base_address) == 0xA381);
 static_assert(GFX6_3D_REG_INDEX(cp_strmout_cntl) == 0xC03F);
+static_assert(GFX6_3D_REG_INDEX(vgt_esgs_ring_size) == 0xC240);
+static_assert(GFX6_3D_REG_INDEX(vgt_gsvs_ring_size) == 0xC241);
 static_assert(GFX6_3D_REG_INDEX(primitive_type) == 0xC242);
 static_assert(GFX6_3D_REG_INDEX(num_instances) == 0xC24D);
 static_assert(GFX6_3D_REG_INDEX(vgt_tf_memory_base) == 0xc250);
diff --git a/src/video_core/amdgpu/regs.h b/src/video_core/amdgpu/regs.h
index a740c38c2..bf5e447cd 100644
--- a/src/video_core/amdgpu/regs.h
+++ b/src/video_core/amdgpu/regs.h
@@ -111,9 +111,12 @@ union Regs {
         TessFactorClamp hs_clamp;
         INSERT_PADDING_WORDS(7);
         GsMode vgt_gs_mode;
-        INSERT_PADDING_WORDS(1);
+        GsOnchip vgt_gs_onchip_control;
         ModeControl mode_control;
-        INSERT_PADDING_WORDS(8);
+        INSERT_PADDING_WORDS(5);
+        RingOffset vgt_gsvs_ring_offset_1;
+        RingOffset vgt_gsvs_ring_offset_2;
+        RingOffset vgt_gsvs_ring_offset_3;
         GsOutPrimitiveType vgt_gs_out_prim_type;
         INSERT_PADDING_WORDS(1);
         u32 index_size;
@@ -147,7 +150,9 @@ union Regs {
         ColorBuffer color_buffers[NUM_COLOR_BUFFERS];
         INSERT_PADDING_WORDS(7343);
         StreamOutControl cp_strmout_cntl;
-        INSERT_PADDING_WORDS(514);
+        INSERT_PADDING_WORDS(512);
+        u32 vgt_esgs_ring_size;
+        u32 vgt_gsvs_ring_size;
         PrimitiveType primitive_type;
         INSERT_PADDING_WORDS(9);
         u32 num_indices;
diff --git a/src/video_core/amdgpu/regs_vertex.h b/src/video_core/amdgpu/regs_vertex.h
index 5422b92c1..a1a1b7a0f 100644
--- a/src/video_core/amdgpu/regs_vertex.h
+++ b/src/video_core/amdgpu/regs_vertex.h
@@ -136,6 +136,17 @@ enum class GsOutputPrimitiveType : u32 {
     TriangleStrip = 2,
 };
 
+union RingOffset {
+    u32 raw;
+    struct {
+        u32 offset : 15;
+    };
+
+    u32 GetOffset() const {
+        return offset;
+    }
+};
+
 union GsOutPrimitiveType {
     u32 raw;
     struct {
@@ -177,11 +188,27 @@ enum class GsScenario : u32 {
 
 struct GsMode {
     GsScenario mode : 3;
+    u32 : 1;
     u32 cut_mode : 2;
-    u32 : 17;
+    u32 : 5;
+    u32 gs_c_pack_en : 1;
+    u32 : 1;
+    u32 es_passthru : 1;
+    u32 compute_mode : 1;
+    u32 fast_compute_mode : 1;
+    u32 element_info_en : 1;
+    u32 partial_thd_at_eoi : 1;
+    u32 suppress_cuts : 1;
+    u32 es_write_optimize : 1;
+    u32 gs_write_optimize : 1;
     u32 onchip : 2;
 };
 
+struct GsOnchip {
+    u32 es_verts_per_subgroup : 11;
+    u32 gs_prims_per_subgroup : 11;
+};
+
 struct StreamOutControl {
     u32 offset_update_done : 1;
     u32 : 31;