mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2026-04-07 09:31:31 -06:00
made cmp_u64 a real u64 compare use it at your own risk
This commit is contained in:
georgemoralis
parent
ab8f4fdfc7
commit
760133c9cc
@ -1136,109 +1136,108 @@ void Translator::V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const
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}
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void Translator::V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst) {
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const bool is_zero = inst.src[1].field == OperandField::ConstZero;
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const bool is_neg_one = inst.src[1].field == OperandField::SignedConstIntNeg;
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const IR::U1 src0 = [&] {
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const IR::U64 src0 = [&]() -> IR::U64 {
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switch (inst.src[0].field) {
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case OperandField::ScalarGPR:
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return ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code));
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case OperandField::VccLo:
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return ir.GetVcc();
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case OperandField::ScalarGPR: {
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IR::U32 low = ir.GetScalarReg(IR::ScalarReg(inst.src[0].code));
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IR::U32 high = ir.GetScalarReg(IR::ScalarReg(inst.src[0].code + 1));
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return ir.PackUint2x32(ir.CompositeConstruct(low, high));
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}
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case OperandField::VectorGPR: {
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IR::U32 low = ir.GetVectorReg(IR::VectorReg(inst.src[0].code));
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IR::U32 high = ir.GetVectorReg(IR::VectorReg(inst.src[0].code + 1));
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return ir.PackUint2x32(ir.CompositeConstruct(low, high));
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}
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case OperandField::VccLo: {
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IR::U1 vcc_bit = ir.GetVcc();
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// Fix: Cast both Imm64 calls to avoid ambiguity
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IR::Value vcc_val =
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ir.Select(vcc_bit, ir.Imm64(static_cast<u64>(-1)), ir.Imm64(static_cast<u64>(0)));
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return IR::U64{vcc_val};
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}
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case OperandField::ConstZero:
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return ir.Imm64(static_cast<u64>(0));
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case OperandField::SignedConstIntPos:
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return ir.Imm64(static_cast<u64>(inst.src[0].code));
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case OperandField::SignedConstIntNeg:
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return ir.Imm64(static_cast<u64>(-s32(inst.src[0].code)));
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default:
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UNREACHABLE_MSG("src0 = {}", u32(inst.src[0].field));
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}
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}();
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// For constant cases
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if (is_zero || is_neg_one) {
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if (is_neg_one) {
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ASSERT_MSG(-s32(inst.src[1].code) + SignedConstIntNegMin - 1 == -1,
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"SignedConstIntNeg must be -1");
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const IR::U64 src1 = [&]() -> IR::U64 {
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switch (inst.src[1].field) {
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case OperandField::ScalarGPR: {
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IR::U32 low = ir.GetScalarReg(IR::ScalarReg(inst.src[1].code));
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IR::U32 high = ir.GetScalarReg(IR::ScalarReg(inst.src[1].code + 1));
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return ir.PackUint2x32(ir.CompositeConstruct(low, high));
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}
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const IR::U1 result = [&] {
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switch (op) {
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case ConditionOp::EQ:
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return is_zero ? ir.LogicalNot(src0) : src0;
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case ConditionOp::LG: // NE
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return is_zero ? src0 : ir.LogicalNot(src0);
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case ConditionOp::GT:
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ASSERT(is_zero);
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return ir.GroupAny(ir.GetThreadBitScalarReg(IR::ScalarReg(inst.src[0].code)));
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default:
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UNREACHABLE_MSG("Unsupported V_CMP_U64 condition operation: {}", u32(op));
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}
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}();
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if (is_signed) {
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UNREACHABLE_MSG("V_CMP_U64 with signed integers is not supported");
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}
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if (set_exec) {
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UNREACHABLE_MSG("Exec setting for V_CMP_U64 is not supported");
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}
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switch (inst.dst[1].field) {
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case OperandField::VccLo:
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return ir.SetVcc(result);
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case OperandField::ScalarGPR:
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return ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[1].code), result);
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default:
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UNREACHABLE();
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}
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return;
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}
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// Handle VectorGPR case - src1 is a 64-bit vector value
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if (inst.src[1].field == OperandField::VectorGPR) {
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// Get the 64-bit vector value from two consecutive VGPRs
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const IR::U32 low = ir.GetVectorReg(IR::VectorReg(inst.src[1].code));
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const IR::U32 high = ir.GetVectorReg(IR::VectorReg(inst.src[1].code + 1));
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const IR::U64 src1_64 =
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ir.PackUint2x32(ir.CompositeConstruct(low, high)); // Combine into 64-bit value
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const IR::Value src0_val = ir.Select(src0, ir.Imm32(1), ir.Imm32(0));
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const IR::U32 src0_32 = IR::U32{src0_val};
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const IR::U64 src0_64 = ir.PackUint2x32(ir.CompositeConstruct(src0_32, ir.Imm32(0U)));
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// Perform the 64-bit comparison
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const IR::U1 result = [&] {
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switch (op) {
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case ConditionOp::EQ:
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return ir.IEqual(src0_64, src1_64);
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case ConditionOp::LG: // NE
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return ir.INotEqual(src0_64, src1_64);
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case ConditionOp::GT:
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return ir.IGreaterThan(src0_64, src1_64, false);
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default:
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UNREACHABLE_MSG("Unsupported V_CMP_U64 condition operation: {}", u32(op));
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}
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}();
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if (is_signed) {
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UNREACHABLE_MSG("V_CMP_U64 with signed integers is not supported");
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}
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if (set_exec) {
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UNREACHABLE_MSG("Exec setting for V_CMP_U64 is not supported");
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}
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switch (inst.dst[1].field) {
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case OperandField::VccLo:
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return ir.SetVcc(result);
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case OperandField::ScalarGPR:
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return ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[1].code), result);
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case OperandField::VectorGPR: {
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IR::Value result_val = ir.Select(result, ir.Imm32(1), ir.Imm32(0));
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ir.SetVectorReg(IR::VectorReg(inst.dst[1].code), IR::U32{result_val});
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} break;
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default:
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UNREACHABLE_MSG("Unsupported dst field: {}", u32(inst.dst[1].field));
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IR::U32 low = ir.GetVectorReg(IR::VectorReg(inst.src[1].code));
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IR::U32 high = ir.GetVectorReg(IR::VectorReg(inst.src[1].code + 1));
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return ir.PackUint2x32(ir.CompositeConstruct(low, high));
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}
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return;
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case OperandField::VccLo: {
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IR::U1 vcc_bit = ir.GetVcc();
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IR::Value vcc_val =
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ir.Select(vcc_bit, ir.Imm64(static_cast<u64>(-1)), ir.Imm64(static_cast<u64>(0)));
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return IR::U64{vcc_val};
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}
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case OperandField::ConstZero:
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return ir.Imm64(static_cast<u64>(0));
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case OperandField::SignedConstIntPos:
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return ir.Imm64(static_cast<u64>(inst.src[1].code));
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case OperandField::SignedConstIntNeg:
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return ir.Imm64(static_cast<u64>(-s32(inst.src[1].code)));
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default:
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UNREACHABLE_MSG("Unsupported src[1] operand field: {}", u32(inst.src[1].field));
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}
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}();
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// Perform the 64-bit comparison
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const IR::U1 result = [&] {
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switch (op) {
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case ConditionOp::EQ:
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return ir.IEqual(src0, src1);
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case ConditionOp::LG: // NE
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return ir.INotEqual(src0, src1);
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case ConditionOp::GT:
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return ir.IGreaterThan(src0, src1, false); // false = unsigned
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case ConditionOp::LT:
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return ir.ILessThan(src0, src1, false);
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case ConditionOp::GE:
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return ir.IGreaterThanEqual(src0, src1, false);
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case ConditionOp::LE:
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return ir.ILessThanEqual(src0, src1, false);
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default:
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UNREACHABLE_MSG("Unsupported V_CMP_U64 condition operation: {}", u32(op));
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}
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}();
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// Handle flags
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if (is_signed) {
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UNREACHABLE_MSG("V_CMP_U64 with signed integers is not supported");
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}
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if (set_exec) {
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UNREACHABLE_MSG("Exec setting for V_CMP_U64 is not supported");
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}
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UNREACHABLE_MSG("Unsupported src[1] operand field for V_CMP_U64: {}", u32(inst.src[1].field));
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// Write result (1-bit boolean) to destination
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switch (inst.dst[1].field) {
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case OperandField::VccLo:
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return ir.SetVcc(result);
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case OperandField::ScalarGPR:
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return ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[1].code), result);
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case OperandField::VectorGPR: {
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IR::Value result_val = ir.Select(result, ir.Imm32(1), ir.Imm32(0));
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ir.SetVectorReg(IR::VectorReg(inst.dst[1].code), IR::U32{result_val});
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} break;
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default:
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UNREACHABLE_MSG("Unsupported dst field: {}", u32(inst.dst[1].field));
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}
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}
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void Translator::V_CMP_CLASS_F32(const GcnInst& inst) {
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const IR::F32 src0{GetSrc<IR::F32>(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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