From dc834f3dbb88ae4d237ee08d009e10adfe677f06 Mon Sep 17 00:00:00 2001 From: Hog Date: Fri, 15 May 2026 09:33:02 +0100 Subject: [PATCH 1/5] add pipeline barriers --- src/video_core/texture_cache/tile_manager.cpp | 77 ++++++++++++++++++- 1 file changed, 76 insertions(+), 1 deletion(-) diff --git a/src/video_core/texture_cache/tile_manager.cpp b/src/video_core/texture_cache/tile_manager.cpp index d80d2db18..707c18614 100644 --- a/src/video_core/texture_cache/tile_manager.cpp +++ b/src/video_core/texture_cache/tile_manager.cpp @@ -194,6 +194,21 @@ TileManager::Result TileManager::DetileImage(vk::Buffer in_buffer, u32 in_offset scheduler.EndRendering(); const auto cmdbuf = scheduler.CommandBuffer(); + + const vk::BufferMemoryBarrier pre_dispatch_barrier{ + .srcAccessMask = vk::AccessFlagBits::eHostWrite | vk::AccessFlagBits::eTransferWrite, + .dstAccessMask = vk::AccessFlagBits::eShaderRead, + .srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .buffer = in_buffer, + .offset = in_offset, + .size = info.guest_size, + }; + cmdbuf.pipelineBarrier( + vk::PipelineStageFlagBits::eHost | vk::PipelineStageFlagBits::eTransfer, + vk::PipelineStageFlagBits::eComputeShader, + {}, {}, pre_dispatch_barrier, {}); + cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, GetTilingPipeline(info, false)); const vk::DescriptorBufferInfo tiled_buffer_info{ @@ -238,6 +253,21 @@ TileManager::Result TileManager::DetileImage(vk::Buffer in_buffer, u32 in_offset const auto dim_x = (info.guest_size / (info.num_bits / 8)) / 64; cmdbuf.dispatch(dim_x, 1, 1); + + const vk::BufferMemoryBarrier post_dispatch_barrier{ + .srcAccessMask = vk::AccessFlagBits::eShaderWrite, + .dstAccessMask = vk::AccessFlagBits::eTransferRead, + .srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .buffer = out_buffer, + .offset = 0, + .size = info.guest_size, + }; + cmdbuf.pipelineBarrier( + vk::PipelineStageFlagBits::eComputeShader, + vk::PipelineStageFlagBits::eTransfer, + {}, {}, post_dispatch_barrier, {}); + return {out_buffer, 0}; } @@ -249,6 +279,21 @@ void TileManager::TileImage(Image& in_image, std::span buff copy.bufferOffset += out_offset; } in_image.Download(buffer_copies, out_buffer, out_offset, copy_size); + + const auto cmdbuf = scheduler.CommandBuffer(); + const vk::BufferMemoryBarrier linear_post_barrier{ + .srcAccessMask = vk::AccessFlagBits::eTransferWrite, + .dstAccessMask = vk::AccessFlagBits::eTransferRead | vk::AccessFlagBits::eHostRead, + .srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .buffer = out_buffer, + .offset = out_offset, + .size = info.guest_size, + }; + cmdbuf.pipelineBarrier( + vk::PipelineStageFlagBits::eTransfer, + vk::PipelineStageFlagBits::eTransfer | vk::PipelineStageFlagBits::eHost, + {}, {}, linear_post_barrier, {}); return; } @@ -276,8 +321,24 @@ void TileManager::TileImage(Image& in_image, std::span buff vmaDestroyBuffer(instance.GetAllocator(), temp_buffer, temp_allocation); }); - const auto cmdbuf = scheduler.CommandBuffer(); + scheduler.EndRendering(); + in_image.Download(buffer_copies, temp_buffer, 0, copy_size); + const auto cmdbuf = scheduler.CommandBuffer(); + + const vk::BufferMemoryBarrier pre_dispatch_barrier{ + .srcAccessMask = vk::AccessFlagBits::eTransferWrite, + .dstAccessMask = vk::AccessFlagBits::eShaderRead, + .srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .buffer = temp_buffer, + .offset = 0, + .size = info.guest_size, + }; + cmdbuf.pipelineBarrier( + vk::PipelineStageFlagBits::eTransfer, + vk::PipelineStageFlagBits::eComputeShader, + {}, {}, pre_dispatch_barrier, {}); cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, GetTilingPipeline(info, true)); @@ -323,6 +384,20 @@ void TileManager::TileImage(Image& in_image, std::span buff const auto dim_x = (info.guest_size / (info.num_bits / 8)) / 64; cmdbuf.dispatch(dim_x, 1, 1); + + const vk::BufferMemoryBarrier post_dispatch_barrier{ + .srcAccessMask = vk::AccessFlagBits::eShaderWrite, + .dstAccessMask = vk::AccessFlagBits::eTransferRead | vk::AccessFlagBits::eHostRead, + .srcQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .dstQueueFamilyIndex = VK_QUEUE_FAMILY_IGNORED, + .buffer = out_buffer, + .offset = out_offset, + .size = info.guest_size, + }; + cmdbuf.pipelineBarrier( + vk::PipelineStageFlagBits::eComputeShader, + vk::PipelineStageFlagBits::eTransfer | vk::PipelineStageFlagBits::eHost, + {}, {}, post_dispatch_barrier, {}); } } // namespace VideoCore From 4095e783e955a435467507db5f83b3d28f21deb8 Mon Sep 17 00:00:00 2001 From: Hog Date: Fri, 15 May 2026 09:49:15 +0100 Subject: [PATCH 2/5] match clangformat --- src/video_core/texture_cache/tile_manager.cpp | 41 +++++++++---------- 1 file changed, 19 insertions(+), 22 deletions(-) diff --git a/src/video_core/texture_cache/tile_manager.cpp b/src/video_core/texture_cache/tile_manager.cpp index 707c18614..8e5052634 100644 --- a/src/video_core/texture_cache/tile_manager.cpp +++ b/src/video_core/texture_cache/tile_manager.cpp @@ -2,6 +2,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later #include "video_core/buffer_cache/buffer.h" +#include "video_core/host_shaders/tiling_comp.h" #include "video_core/renderer_vulkan/vk_instance.h" #include "video_core/renderer_vulkan/vk_scheduler.h" #include "video_core/renderer_vulkan/vk_shader_util.h" @@ -10,8 +11,6 @@ #include "video_core/texture_cache/image_view.h" #include "video_core/texture_cache/tile_manager.h" -#include "video_core/host_shaders/tiling_comp.h" - #include #include @@ -125,8 +124,9 @@ vk::Pipeline TileManager::GetTilingPipeline(const ImageInfo& info, bool is_tiler defines.emplace_back(fmt::format("NUM_BANKS={}", num_banks)); defines.emplace_back(fmt::format("NUM_BANK_BITS={}", std::bit_width(num_banks) - 1)); defines.emplace_back(fmt::format( - "TILE_SPLIT_BYTES={}", AmdGpu::CalculateTileSplit(info.tile_mode, info.array_mode, - micro_tile_mode, info.num_bits))); + "TILE_SPLIT_BYTES={}", AmdGpu::CalculateTileSplit( + info.tile_mode, info.array_mode, micro_tile_mode, + info.num_bits))); defines.emplace_back( fmt::format("MACRO_TILE_ASPECT={}", AmdGpu::GetMacrotileAspect(macro_tile_mode))); } @@ -206,8 +206,7 @@ TileManager::Result TileManager::DetileImage(vk::Buffer in_buffer, u32 in_offset }; cmdbuf.pipelineBarrier( vk::PipelineStageFlagBits::eHost | vk::PipelineStageFlagBits::eTransfer, - vk::PipelineStageFlagBits::eComputeShader, - {}, {}, pre_dispatch_barrier, {}); + vk::PipelineStageFlagBits::eComputeShader, {}, {}, pre_dispatch_barrier, {}); cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, GetTilingPipeline(info, false)); @@ -263,10 +262,9 @@ TileManager::Result TileManager::DetileImage(vk::Buffer in_buffer, u32 in_offset .offset = 0, .size = info.guest_size, }; - cmdbuf.pipelineBarrier( - vk::PipelineStageFlagBits::eComputeShader, - vk::PipelineStageFlagBits::eTransfer, - {}, {}, post_dispatch_barrier, {}); + cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eComputeShader, + vk::PipelineStageFlagBits::eTransfer, {}, {}, post_dispatch_barrier, + {}); return {out_buffer, 0}; } @@ -290,10 +288,10 @@ void TileManager::TileImage(Image& in_image, std::span buff .offset = out_offset, .size = info.guest_size, }; - cmdbuf.pipelineBarrier( - vk::PipelineStageFlagBits::eTransfer, - vk::PipelineStageFlagBits::eTransfer | vk::PipelineStageFlagBits::eHost, - {}, {}, linear_post_barrier, {}); + cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eTransfer, + vk::PipelineStageFlagBits::eTransfer | + vk::PipelineStageFlagBits::eHost, + {}, {}, linear_post_barrier, {}); return; } @@ -335,10 +333,9 @@ void TileManager::TileImage(Image& in_image, std::span buff .offset = 0, .size = info.guest_size, }; - cmdbuf.pipelineBarrier( - vk::PipelineStageFlagBits::eTransfer, - vk::PipelineStageFlagBits::eComputeShader, - {}, {}, pre_dispatch_barrier, {}); + cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eTransfer, + vk::PipelineStageFlagBits::eComputeShader, {}, {}, + pre_dispatch_barrier, {}); cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, GetTilingPipeline(info, true)); @@ -394,10 +391,10 @@ void TileManager::TileImage(Image& in_image, std::span buff .offset = out_offset, .size = info.guest_size, }; - cmdbuf.pipelineBarrier( - vk::PipelineStageFlagBits::eComputeShader, - vk::PipelineStageFlagBits::eTransfer | vk::PipelineStageFlagBits::eHost, - {}, {}, post_dispatch_barrier, {}); + cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eComputeShader, + vk::PipelineStageFlagBits::eTransfer | + vk::PipelineStageFlagBits::eHost, + {}, {}, post_dispatch_barrier, {}); } } // namespace VideoCore From 617f704f6c01676d7b28b83212796c6cb3e6b9e8 Mon Sep 17 00:00:00 2001 From: Hog Date: Fri, 15 May 2026 10:10:29 +0100 Subject: [PATCH 3/5] uhm, let me be formatted --- src/video_core/texture_cache/tile_manager.cpp | 32 +++++++++---------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/src/video_core/texture_cache/tile_manager.cpp b/src/video_core/texture_cache/tile_manager.cpp index 8e5052634..2c8240e90 100644 --- a/src/video_core/texture_cache/tile_manager.cpp +++ b/src/video_core/texture_cache/tile_manager.cpp @@ -1,6 +1,9 @@ // SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project // SPDX-License-Identifier: GPL-2.0-or-later +#include +#include + #include "video_core/buffer_cache/buffer.h" #include "video_core/host_shaders/tiling_comp.h" #include "video_core/renderer_vulkan/vk_instance.h" @@ -11,9 +14,6 @@ #include "video_core/texture_cache/image_view.h" #include "video_core/texture_cache/tile_manager.h" -#include -#include - namespace VideoCore { struct TilingInfo { @@ -124,9 +124,9 @@ vk::Pipeline TileManager::GetTilingPipeline(const ImageInfo& info, bool is_tiler defines.emplace_back(fmt::format("NUM_BANKS={}", num_banks)); defines.emplace_back(fmt::format("NUM_BANK_BITS={}", std::bit_width(num_banks) - 1)); defines.emplace_back(fmt::format( - "TILE_SPLIT_BYTES={}", AmdGpu::CalculateTileSplit( - info.tile_mode, info.array_mode, micro_tile_mode, - info.num_bits))); + "TILE_SPLIT_BYTES={}", + AmdGpu::CalculateTileSplit(info.tile_mode, info.array_mode, micro_tile_mode, + info.num_bits))); defines.emplace_back( fmt::format("MACRO_TILE_ASPECT={}", AmdGpu::GetMacrotileAspect(macro_tile_mode))); } @@ -164,7 +164,7 @@ vk::Pipeline TileManager::GetTilingPipeline(const ImageInfo& info, bool is_tiler TileManager::Result TileManager::DetileImage(vk::Buffer in_buffer, u32 in_offset, const ImageInfo& info) { if (!info.props.is_tiled) { - return {in_buffer, in_offset}; + return { in_buffer, in_offset }; } TilingInfo params{}; @@ -204,9 +204,9 @@ TileManager::Result TileManager::DetileImage(vk::Buffer in_buffer, u32 in_offset .offset = in_offset, .size = info.guest_size, }; - cmdbuf.pipelineBarrier( - vk::PipelineStageFlagBits::eHost | vk::PipelineStageFlagBits::eTransfer, - vk::PipelineStageFlagBits::eComputeShader, {}, {}, pre_dispatch_barrier, {}); + cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eHost | vk::PipelineStageFlagBits::eTransfer, + vk::PipelineStageFlagBits::eComputeShader, {}, {}, pre_dispatch_barrier, + {}); cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, GetTilingPipeline(info, false)); @@ -263,10 +263,9 @@ TileManager::Result TileManager::DetileImage(vk::Buffer in_buffer, u32 in_offset .size = info.guest_size, }; cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eComputeShader, - vk::PipelineStageFlagBits::eTransfer, {}, {}, post_dispatch_barrier, - {}); + vk::PipelineStageFlagBits::eTransfer, {}, {}, post_dispatch_barrier, {}); - return {out_buffer, 0}; + return { out_buffer, 0 }; } void TileManager::TileImage(Image& in_image, std::span buffer_copies, @@ -334,8 +333,8 @@ void TileManager::TileImage(Image& in_image, std::span buff .size = info.guest_size, }; cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eTransfer, - vk::PipelineStageFlagBits::eComputeShader, {}, {}, - pre_dispatch_barrier, {}); + vk::PipelineStageFlagBits::eComputeShader, {}, {}, pre_dispatch_barrier, + {}); cmdbuf.bindPipeline(vk::PipelineBindPoint::eCompute, GetTilingPipeline(info, true)); @@ -392,8 +391,7 @@ void TileManager::TileImage(Image& in_image, std::span buff .size = info.guest_size, }; cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eComputeShader, - vk::PipelineStageFlagBits::eTransfer | - vk::PipelineStageFlagBits::eHost, + vk::PipelineStageFlagBits::eTransfer | vk::PipelineStageFlagBits::eHost, {}, {}, post_dispatch_barrier, {}); } From 64e3676b90900eb99a63aa791162fb790546ad67 Mon Sep 17 00:00:00 2001 From: Hog Date: Fri, 15 May 2026 10:13:09 +0100 Subject: [PATCH 4/5] FUCK TS --- src/video_core/texture_cache/tile_manager.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/video_core/texture_cache/tile_manager.cpp b/src/video_core/texture_cache/tile_manager.cpp index 2c8240e90..647975c1e 100644 --- a/src/video_core/texture_cache/tile_manager.cpp +++ b/src/video_core/texture_cache/tile_manager.cpp @@ -72,6 +72,7 @@ TileManager::TileManager(const Vulkan::Instance& instance, Vulkan::Scheduler& sc pl_layout = std::move(layout); } +// NOLINTNEXTLINE(performance-trivially-destructible) TileManager::~TileManager() = default; TileManager::ScratchBuffer TileManager::GetScratchBuffer(u32 size) { @@ -124,9 +125,8 @@ vk::Pipeline TileManager::GetTilingPipeline(const ImageInfo& info, bool is_tiler defines.emplace_back(fmt::format("NUM_BANKS={}", num_banks)); defines.emplace_back(fmt::format("NUM_BANK_BITS={}", std::bit_width(num_banks) - 1)); defines.emplace_back(fmt::format( - "TILE_SPLIT_BYTES={}", - AmdGpu::CalculateTileSplit(info.tile_mode, info.array_mode, micro_tile_mode, - info.num_bits))); + "TILE_SPLIT_BYTES={}", AmdGpu::CalculateTileSplit(info.tile_mode, info.array_mode, + micro_tile_mode, info.num_bits))); defines.emplace_back( fmt::format("MACRO_TILE_ASPECT={}", AmdGpu::GetMacrotileAspect(macro_tile_mode))); } @@ -164,7 +164,7 @@ vk::Pipeline TileManager::GetTilingPipeline(const ImageInfo& info, bool is_tiler TileManager::Result TileManager::DetileImage(vk::Buffer in_buffer, u32 in_offset, const ImageInfo& info) { if (!info.props.is_tiled) { - return { in_buffer, in_offset }; + return {in_buffer, in_offset}; } TilingInfo params{}; @@ -265,7 +265,7 @@ TileManager::Result TileManager::DetileImage(vk::Buffer in_buffer, u32 in_offset cmdbuf.pipelineBarrier(vk::PipelineStageFlagBits::eComputeShader, vk::PipelineStageFlagBits::eTransfer, {}, {}, post_dispatch_barrier, {}); - return { out_buffer, 0 }; + return {out_buffer, 0}; } void TileManager::TileImage(Image& in_image, std::span buffer_copies, From 6b2c17ac197921b0830511371aea4c1a81690ce8 Mon Sep 17 00:00:00 2001 From: Hog Date: Fri, 15 May 2026 10:24:19 +0100 Subject: [PATCH 5/5] MEOW M EOW MEPW EW KEMOPWEKRKJNQ2WKXCJWENKLDKPL; --- src/video_core/texture_cache/tile_manager.cpp | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/video_core/texture_cache/tile_manager.cpp b/src/video_core/texture_cache/tile_manager.cpp index 647975c1e..7bf08a3c7 100644 --- a/src/video_core/texture_cache/tile_manager.cpp +++ b/src/video_core/texture_cache/tile_manager.cpp @@ -1,9 +1,6 @@ // SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project // SPDX-License-Identifier: GPL-2.0-or-later -#include -#include - #include "video_core/buffer_cache/buffer.h" #include "video_core/host_shaders/tiling_comp.h" #include "video_core/renderer_vulkan/vk_instance.h" @@ -14,6 +11,9 @@ #include "video_core/texture_cache/image_view.h" #include "video_core/texture_cache/tile_manager.h" +#include +#include + namespace VideoCore { struct TilingInfo { @@ -72,7 +72,6 @@ TileManager::TileManager(const Vulkan::Instance& instance, Vulkan::Scheduler& sc pl_layout = std::move(layout); } -// NOLINTNEXTLINE(performance-trivially-destructible) TileManager::~TileManager() = default; TileManager::ScratchBuffer TileManager::GetScratchBuffer(u32 size) {