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Merge 4c97c2ff51 into d7ccf25e6f

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Xupie 2026-06-10 00:45:31 +05:00 committed by GitHub
commit c98bfe4e95
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7 changed files with 41 additions and 1 deletions
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12
src/shader_recompiler/backend/spirv/emit_spirv.cpp
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@ -663,6 +663,18 @@ void EmitGetExec(EmitContext& ctx) {
UNREACHABLE_MSG("Unreachable instruction");
}
Id EmitGetExecLo(EmitContext& ctx) {
const Id scope_subgroup = ctx.ConstU32(static_cast<u32>(spv::Scope::Subgroup));
const Id ballot = ctx.OpGroupNonUniformBallot(ctx.U32[4], scope_subgroup, ctx.true_value);
return ctx.OpCompositeExtract(ctx.U32[1], ballot, 0u);
}
Id EmitGetExecHi(EmitContext& ctx) {
const Id scope_subgroup = ctx.ConstU32(static_cast<u32>(spv::Scope::Subgroup));
const Id ballot = ctx.OpGroupNonUniformBallot(ctx.U32[4], scope_subgroup, ctx.true_value);
return ctx.OpCompositeExtract(ctx.U32[1], ballot, 1u);
}
void EmitGetVcc(EmitContext& ctx) {
UNREACHABLE_MSG("Unreachable instruction");
}

2
src/shader_recompiler/backend/spirv/emit_spirv_instructions.h
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@ -30,6 +30,8 @@ void EmitPhiMove(EmitContext&);
void EmitJoin(EmitContext& ctx);
void EmitGetScc(EmitContext& ctx);
void EmitGetExec(EmitContext& ctx);
Id EmitGetExecLo(EmitContext& ctx);
Id EmitGetExecHi(EmitContext& ctx);
void EmitGetVcc(EmitContext& ctx);
void EmitGetSccLo(EmitContext& ctx);
void EmitGetVccLo(EmitContext& ctx);

2
src/shader_recompiler/frontend/opcodes.h
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@ -2565,7 +2565,7 @@ enum class OperandField : u32 {
VccHi,
M0 = 124,
ExecLo = 126,
ExecHi,
ExecHi = 127,
ConstZero,
SignedConstIntPos = 129,
SignedConstIntNeg = 193,

14
src/shader_recompiler/frontend/translate/translate.cpp
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@ -341,6 +341,20 @@ T Translator::GetSrc(const InstOperand& operand) {
UNREACHABLE_MSG("unhandled SDWA");
case OperandField::Dpp:
UNREACHABLE_MSG("unhandled DPP");
case OperandField::ExecLo:
if constexpr (is_float) {
value = ir.BitCast<IR::F32>(ir.GetExecLo());
} else {
value = ir.GetExecLo();
}
break;
case OperandField::ExecHi:
if constexpr (is_float) {
value = ir.BitCast<IR::F32>(ir.GetExecHi());
} else {
value = ir.GetExecHi();
}
break;
case OperandField::VccLo:
if constexpr (is_float) {
value = ir.BitCast<IR::F32>(ir.GetVccLo());

8
src/shader_recompiler/ir/ir_emitter.cpp
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@ -210,6 +210,14 @@ U1 IREmitter::GetExec() {
return Inst<U1>(Opcode::GetExec);
}
U32 IREmitter::GetExecLo() {
return Inst<U32>(Opcode::GetExecLo);
}
U32 IREmitter::GetExecHi() {
return Inst<U32>(Opcode::GetExecHi);
}
U1 IREmitter::GetVcc() {
return Inst<U1>(Opcode::GetVcc);
}

2
src/shader_recompiler/ir/ir_emitter.h
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@ -67,6 +67,8 @@ public:
[[nodiscard]] U1 GetScc();
[[nodiscard]] U1 GetExec();
[[nodiscard]] U32 GetExecLo();
[[nodiscard]] U32 GetExecHi();
[[nodiscard]] U1 GetVcc();
[[nodiscard]] U32 GetVccLo();
[[nodiscard]] U32 GetVccHi();

2
src/shader_recompiler/ir/opcodes.inc
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@ -84,6 +84,8 @@ OPCODE(ReadTcsGenericOuputAttribute, F32, U32,
// Flags
OPCODE(GetScc, U1, Void, )
OPCODE(GetExec, U1, Void, )
OPCODE(GetExecLo, U32, Void, )
OPCODE(GetExecHi, U32, Void, )
OPCODE(GetVcc, U1, Void, )
OPCODE(GetVccLo, U32, Void, )
OPCODE(GetVccHi, U32, Void, )