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https://github.com/shadps4-emu/shadPS4.git
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0d3b6f7dd0
* resource_tracking_pass: Adjust buffer type if host doesn't support float buffer atomic * resource_tracking_pass: Implement data append/consume as buffer atomics in IR level This was previously done in spirv backend, the implementation was exactly the same as the buffer atomics, so unify them * ir: Bump instruction flag to 8 bytes * frontend: Pass pc to buffer flags for better debugging when sharp tracking fails * clang format --------- Co-authored-by: georgemoralis <giorgosmrls@gmail.com>
88 lines
3.0 KiB
C++
88 lines
3.0 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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namespace Shader::Gcn {
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static constexpr u32 SQ_SRC_LITERAL = 0xFF;
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void Translator::EmitScalarMemory(const GcnInst& inst) {
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switch (inst.opcode) {
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// SMRD
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case Opcode::S_LOAD_DWORD:
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return S_LOAD_DWORD(1, inst);
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case Opcode::S_LOAD_DWORDX2:
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return S_LOAD_DWORD(2, inst);
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case Opcode::S_LOAD_DWORDX4:
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return S_LOAD_DWORD(4, inst);
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case Opcode::S_LOAD_DWORDX8:
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return S_LOAD_DWORD(8, inst);
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case Opcode::S_LOAD_DWORDX16:
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return S_LOAD_DWORD(16, inst);
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case Opcode::S_BUFFER_LOAD_DWORD:
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return S_BUFFER_LOAD_DWORD(1, inst);
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case Opcode::S_BUFFER_LOAD_DWORDX2:
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return S_BUFFER_LOAD_DWORD(2, inst);
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case Opcode::S_BUFFER_LOAD_DWORDX4:
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return S_BUFFER_LOAD_DWORD(4, inst);
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case Opcode::S_BUFFER_LOAD_DWORDX8:
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return S_BUFFER_LOAD_DWORD(8, inst);
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case Opcode::S_BUFFER_LOAD_DWORDX16:
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return S_BUFFER_LOAD_DWORD(16, inst);
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default:
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LogMissingOpcode(inst);
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}
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}
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// SMRD
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void Translator::S_LOAD_DWORD(int num_dwords, const GcnInst& inst) {
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const auto& smrd = inst.control.smrd;
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const IR::ScalarReg sbase{inst.src[0].code * 2};
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const IR::U32 dword_offset = [&] -> IR::U32 {
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if (smrd.imm) {
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return ir.Imm32(smrd.offset);
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}
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if (smrd.offset == SQ_SRC_LITERAL) {
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return ir.Imm32(inst.src[1].code);
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}
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return ir.ShiftRightLogical(ir.GetScalarReg(IR::ScalarReg(smrd.offset)), ir.Imm32(2));
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}();
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const IR::Value base =
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ir.CompositeConstruct(ir.GetScalarReg(sbase), ir.GetScalarReg(sbase + 1));
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IR::ScalarReg dst_reg{inst.dst[0].code};
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for (u32 i = 0; i < num_dwords; i++) {
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IR::U32 index = ir.IAdd(dword_offset, ir.Imm32(i));
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ir.SetScalarReg(dst_reg + i, ir.ReadConst(base, index));
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}
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}
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void Translator::S_BUFFER_LOAD_DWORD(int num_dwords, const GcnInst& inst) {
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const auto& smrd = inst.control.smrd;
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const IR::ScalarReg sbase{inst.src[0].code * 2};
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const IR::U32 dword_offset = [&] -> IR::U32 {
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if (smrd.imm) {
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return ir.Imm32(smrd.offset);
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}
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if (smrd.offset == SQ_SRC_LITERAL) {
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return ir.Imm32(inst.src[1].code);
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}
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return ir.ShiftRightLogical(ir.GetScalarReg(IR::ScalarReg(smrd.offset)), ir.Imm32(2));
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}();
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IR::BufferInstInfo buffer_info{};
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buffer_info.pc.Assign(pc);
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const IR::Value vsharp =
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ir.CompositeConstruct(ir.GetScalarReg(sbase), ir.GetScalarReg(sbase + 1),
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ir.GetScalarReg(sbase + 2), ir.GetScalarReg(sbase + 3));
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IR::ScalarReg dst_reg{inst.dst[0].code};
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for (u32 i = 0; i < num_dwords; i++) {
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const IR::U32 index = ir.IAdd(dword_offset, ir.Imm32(i));
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ir.SetScalarReg(dst_reg + i, ir.ReadConstBuffer(vsharp, index, buffer_info));
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}
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}
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} // namespace Shader::Gcn
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