mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2026-04-02 19:08:03 -06:00
85476e55ea
* To implement ImageAtomicCmpSwap ...but it doesn't work, so here it shall stay. * a fix * Clang * Add to MayHaveSideEffects I missed this while digging through IR code.
702 lines
28 KiB
C++
702 lines
28 KiB
C++
// SPDX-FileCopyrightText: Copyright 2024 shadPS4 Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "shader_recompiler/frontend/translate/translate.h"
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namespace Shader::Gcn {
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void Translator::EmitVectorMemory(const GcnInst& inst) {
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switch (inst.opcode) {
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// MUBUF / MTBUF
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// Buffer load operations
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case Opcode::TBUFFER_LOAD_FORMAT_X:
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return BUFFER_LOAD(1, true, false, inst);
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case Opcode::TBUFFER_LOAD_FORMAT_XY:
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return BUFFER_LOAD(2, true, false, inst);
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case Opcode::TBUFFER_LOAD_FORMAT_XYZ:
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return BUFFER_LOAD(3, true, false, inst);
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case Opcode::TBUFFER_LOAD_FORMAT_XYZW:
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return BUFFER_LOAD(4, true, false, inst);
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case Opcode::BUFFER_LOAD_FORMAT_X:
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return BUFFER_LOAD(1, false, true, inst);
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case Opcode::BUFFER_LOAD_FORMAT_XY:
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return BUFFER_LOAD(2, false, true, inst);
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case Opcode::BUFFER_LOAD_FORMAT_XYZ:
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return BUFFER_LOAD(3, false, true, inst);
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case Opcode::BUFFER_LOAD_FORMAT_XYZW:
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return BUFFER_LOAD(4, false, true, inst);
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case Opcode::BUFFER_LOAD_UBYTE:
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return BUFFER_LOAD(1, false, false, inst, 8, false);
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case Opcode::BUFFER_LOAD_SBYTE:
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return BUFFER_LOAD(1, false, false, inst, 8, true);
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case Opcode::BUFFER_LOAD_USHORT:
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return BUFFER_LOAD(1, false, false, inst, 16, false);
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case Opcode::BUFFER_LOAD_SSHORT:
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return BUFFER_LOAD(1, false, false, inst, 16, true);
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case Opcode::BUFFER_LOAD_DWORD:
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return BUFFER_LOAD(1, false, false, inst);
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case Opcode::BUFFER_LOAD_DWORDX2:
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return BUFFER_LOAD(2, false, false, inst);
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case Opcode::BUFFER_LOAD_DWORDX3:
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return BUFFER_LOAD(3, false, false, inst);
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case Opcode::BUFFER_LOAD_DWORDX4:
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return BUFFER_LOAD(4, false, false, inst);
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// Buffer store operations
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case Opcode::BUFFER_STORE_FORMAT_X:
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return BUFFER_STORE(1, false, true, inst);
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case Opcode::BUFFER_STORE_FORMAT_XY:
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return BUFFER_STORE(2, false, true, inst);
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case Opcode::BUFFER_STORE_FORMAT_XYZ:
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return BUFFER_STORE(3, false, true, inst);
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case Opcode::BUFFER_STORE_FORMAT_XYZW:
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return BUFFER_STORE(4, false, true, inst);
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case Opcode::TBUFFER_STORE_FORMAT_X:
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return BUFFER_STORE(1, true, false, inst);
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case Opcode::TBUFFER_STORE_FORMAT_XY:
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return BUFFER_STORE(2, true, false, inst);
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case Opcode::TBUFFER_STORE_FORMAT_XYZ:
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return BUFFER_STORE(3, true, false, inst);
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case Opcode::TBUFFER_STORE_FORMAT_XYZW:
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return BUFFER_STORE(4, true, false, inst);
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case Opcode::BUFFER_STORE_BYTE:
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return BUFFER_STORE(1, false, false, inst, 8);
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case Opcode::BUFFER_STORE_SHORT:
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return BUFFER_STORE(1, false, false, inst, 16);
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case Opcode::BUFFER_STORE_DWORD:
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return BUFFER_STORE(1, false, false, inst);
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case Opcode::BUFFER_STORE_DWORDX2:
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return BUFFER_STORE(2, false, false, inst);
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case Opcode::BUFFER_STORE_DWORDX3:
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return BUFFER_STORE(3, false, false, inst);
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case Opcode::BUFFER_STORE_DWORDX4:
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return BUFFER_STORE(4, false, false, inst);
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// Buffer atomic operations
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case Opcode::BUFFER_ATOMIC_ADD:
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return BUFFER_ATOMIC(AtomicOp::Add, inst);
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case Opcode::BUFFER_ATOMIC_SWAP:
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return BUFFER_ATOMIC(AtomicOp::Swap, inst);
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case Opcode::BUFFER_ATOMIC_CMPSWAP:
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return BUFFER_ATOMIC(AtomicOp::CmpSwap, inst);
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case Opcode::BUFFER_ATOMIC_SMIN:
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return BUFFER_ATOMIC(AtomicOp::Smin, inst);
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case Opcode::BUFFER_ATOMIC_SMIN_X2:
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return BUFFER_ATOMIC<IR::U64>(AtomicOp::Smin, inst);
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case Opcode::BUFFER_ATOMIC_UMIN:
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return BUFFER_ATOMIC(AtomicOp::Umin, inst);
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case Opcode::BUFFER_ATOMIC_UMIN_X2:
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return BUFFER_ATOMIC<IR::U64>(AtomicOp::Umin, inst);
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case Opcode::BUFFER_ATOMIC_SMAX:
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return BUFFER_ATOMIC(AtomicOp::Smax, inst);
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case Opcode::BUFFER_ATOMIC_SMAX_X2:
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return BUFFER_ATOMIC<IR::U64>(AtomicOp::Smax, inst);
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case Opcode::BUFFER_ATOMIC_UMAX:
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return BUFFER_ATOMIC(AtomicOp::Umax, inst);
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case Opcode::BUFFER_ATOMIC_UMAX_X2:
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return BUFFER_ATOMIC<IR::U64>(AtomicOp::Umax, inst);
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case Opcode::BUFFER_ATOMIC_AND:
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return BUFFER_ATOMIC(AtomicOp::And, inst);
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case Opcode::BUFFER_ATOMIC_OR:
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return BUFFER_ATOMIC(AtomicOp::Or, inst);
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case Opcode::BUFFER_ATOMIC_XOR:
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return BUFFER_ATOMIC(AtomicOp::Xor, inst);
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case Opcode::BUFFER_ATOMIC_INC:
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return BUFFER_ATOMIC(AtomicOp::Inc, inst);
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case Opcode::BUFFER_ATOMIC_DEC:
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return BUFFER_ATOMIC(AtomicOp::Dec, inst);
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case Opcode::BUFFER_ATOMIC_FMIN:
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return BUFFER_ATOMIC<IR::F32>(AtomicOp::Fmin, inst);
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case Opcode::BUFFER_ATOMIC_FMAX:
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return BUFFER_ATOMIC<IR::F32>(AtomicOp::Fmax, inst);
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// MIMG
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// Image load operations
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case Opcode::IMAGE_LOAD:
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return IMAGE_LOAD(false, inst);
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case Opcode::IMAGE_LOAD_MIP:
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return IMAGE_LOAD(true, inst);
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// Buffer store operations
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case Opcode::IMAGE_STORE:
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return IMAGE_STORE(false, inst);
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case Opcode::IMAGE_STORE_MIP:
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return IMAGE_STORE(true, inst);
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// Image misc operations
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case Opcode::IMAGE_GET_RESINFO:
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return IMAGE_GET_RESINFO(inst);
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// Image atomic operations
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case Opcode::IMAGE_ATOMIC_SWAP:
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return IMAGE_ATOMIC(AtomicOp::Swap, inst);
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case Opcode::IMAGE_ATOMIC_CMPSWAP:
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return IMAGE_ATOMIC(AtomicOp::CmpSwap, inst);
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case Opcode::IMAGE_ATOMIC_ADD:
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return IMAGE_ATOMIC(AtomicOp::Add, inst);
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case Opcode::IMAGE_ATOMIC_SMIN:
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return IMAGE_ATOMIC(AtomicOp::Smin, inst);
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case Opcode::IMAGE_ATOMIC_UMIN:
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return IMAGE_ATOMIC(AtomicOp::Umin, inst);
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case Opcode::IMAGE_ATOMIC_FMIN:
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return IMAGE_ATOMIC(AtomicOp::Fmin, inst);
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case Opcode::IMAGE_ATOMIC_SMAX:
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return IMAGE_ATOMIC(AtomicOp::Smax, inst);
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case Opcode::IMAGE_ATOMIC_FMAX:
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return IMAGE_ATOMIC(AtomicOp::Fmax, inst);
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case Opcode::IMAGE_ATOMIC_UMAX:
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return IMAGE_ATOMIC(AtomicOp::Umax, inst);
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case Opcode::IMAGE_ATOMIC_AND:
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return IMAGE_ATOMIC(AtomicOp::And, inst);
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case Opcode::IMAGE_ATOMIC_OR:
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return IMAGE_ATOMIC(AtomicOp::Or, inst);
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case Opcode::IMAGE_ATOMIC_XOR:
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return IMAGE_ATOMIC(AtomicOp::Xor, inst);
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case Opcode::IMAGE_ATOMIC_INC:
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return IMAGE_ATOMIC(AtomicOp::Inc, inst);
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case Opcode::IMAGE_ATOMIC_DEC:
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return IMAGE_ATOMIC(AtomicOp::Dec, inst);
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case Opcode::IMAGE_SAMPLE:
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case Opcode::IMAGE_SAMPLE_D:
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case Opcode::IMAGE_SAMPLE_L:
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case Opcode::IMAGE_SAMPLE_B:
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case Opcode::IMAGE_SAMPLE_LZ:
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case Opcode::IMAGE_SAMPLE_C:
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case Opcode::IMAGE_SAMPLE_C_LZ:
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case Opcode::IMAGE_SAMPLE_O:
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case Opcode::IMAGE_SAMPLE_L_O:
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case Opcode::IMAGE_SAMPLE_B_O:
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case Opcode::IMAGE_SAMPLE_LZ_O:
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case Opcode::IMAGE_SAMPLE_C_O:
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case Opcode::IMAGE_SAMPLE_C_LZ_O:
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case Opcode::IMAGE_SAMPLE_CD:
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return IMAGE_SAMPLE(inst);
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// Image gather operations
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case Opcode::IMAGE_GATHER4:
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case Opcode::IMAGE_GATHER4_L:
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case Opcode::IMAGE_GATHER4_LZ:
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case Opcode::IMAGE_GATHER4_C:
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case Opcode::IMAGE_GATHER4_O:
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case Opcode::IMAGE_GATHER4_C_O:
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case Opcode::IMAGE_GATHER4_C_LZ:
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case Opcode::IMAGE_GATHER4_LZ_O:
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case Opcode::IMAGE_GATHER4_C_LZ_O:
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return IMAGE_GATHER(inst);
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// Image misc operations
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case Opcode::IMAGE_GET_LOD:
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return IMAGE_GET_LOD(inst);
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default:
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LogMissingOpcode(inst);
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}
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}
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void Translator::BUFFER_LOAD(u32 num_dwords, bool is_inst_typed, bool is_buffer_typed,
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const GcnInst& inst, u32 scalar_width, bool is_signed) {
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const auto& mubuf = inst.control.mubuf;
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const IR::VectorReg vaddr{inst.src[0].code};
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const IR::ScalarReg sharp{inst.src[2].code * 4};
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const IR::U32 index = mubuf.idxen ? ir.GetVectorReg(vaddr) : ir.Imm32(0);
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const IR::VectorReg voffset_vgpr = mubuf.idxen ? vaddr + 1 : vaddr;
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const IR::U32 voffset = mubuf.offen ? ir.GetVectorReg(voffset_vgpr) : ir.Imm32(0);
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const IR::U32 soffset{GetSrc(inst.src[3])};
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const IR::Value address = ir.CompositeConstruct(index, voffset, soffset);
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IR::BufferInstInfo buffer_info{};
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buffer_info.index_enable.Assign(mubuf.idxen);
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buffer_info.voffset_enable.Assign(mubuf.offen);
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buffer_info.inst_offset.Assign(mubuf.offset);
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buffer_info.globally_coherent.Assign(mubuf.glc);
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buffer_info.system_coherent.Assign(mubuf.slc);
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buffer_info.typed.Assign(is_inst_typed || is_buffer_typed);
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if (is_inst_typed) {
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const auto& mtbuf = inst.control.mtbuf;
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buffer_info.inst_data_fmt.Assign(static_cast<AmdGpu::DataFormat>(mtbuf.dfmt));
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buffer_info.inst_num_fmt.Assign(static_cast<AmdGpu::NumberFormat>(mtbuf.nfmt));
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} else {
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buffer_info.inst_data_fmt.Assign(AmdGpu::DataFormat::FormatInvalid);
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}
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const IR::Value handle =
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ir.CompositeConstruct(ir.GetScalarReg(sharp), ir.GetScalarReg(sharp + 1),
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ir.GetScalarReg(sharp + 2), ir.GetScalarReg(sharp + 3));
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const IR::VectorReg dst_reg{inst.src[1].code};
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if (buffer_info.typed) {
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const IR::Value value = ir.LoadBufferFormat(handle, address, buffer_info);
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for (u32 i = 0; i < num_dwords; i++) {
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ir.SetVectorReg(dst_reg + i, IR::F32{ir.CompositeExtract(value, i)});
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}
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} else {
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IR::Value value;
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switch (scalar_width) {
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case 8: {
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IR::U8 byte_val = ir.LoadBufferU8(handle, address, buffer_info);
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value = is_signed ? ir.SConvert(32, byte_val) : ir.UConvert(32, byte_val);
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break;
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}
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case 16: {
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IR::U16 short_val = ir.LoadBufferU16(handle, address, buffer_info);
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value = is_signed ? ir.SConvert(32, short_val) : ir.UConvert(32, short_val);
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break;
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}
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case 32:
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value = ir.LoadBufferU32(num_dwords, handle, address, buffer_info);
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break;
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default:
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UNREACHABLE();
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}
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if (num_dwords == 1) {
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ir.SetVectorReg(dst_reg, IR::U32{value});
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return;
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}
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for (u32 i = 0; i < num_dwords; i++) {
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ir.SetVectorReg(dst_reg + i, IR::U32{ir.CompositeExtract(value, i)});
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}
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}
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}
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void Translator::BUFFER_STORE(u32 num_dwords, bool is_inst_typed, bool is_buffer_typed,
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const GcnInst& inst, u32 scalar_width) {
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const auto& mubuf = inst.control.mubuf;
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const IR::VectorReg vaddr{inst.src[0].code};
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const IR::ScalarReg sharp{inst.src[2].code * 4};
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const IR::U32 index = mubuf.idxen ? ir.GetVectorReg(vaddr) : ir.Imm32(0);
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const IR::VectorReg voffset_vgpr = mubuf.idxen ? vaddr + 1 : vaddr;
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const IR::U32 voffset = mubuf.offen ? ir.GetVectorReg(voffset_vgpr) : ir.Imm32(0);
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const IR::U32 soffset{GetSrc(inst.src[3])};
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const IR::Value address = ir.CompositeConstruct(index, voffset, soffset);
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IR::BufferInstInfo buffer_info{};
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buffer_info.index_enable.Assign(mubuf.idxen);
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buffer_info.voffset_enable.Assign(mubuf.offen);
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buffer_info.inst_offset.Assign(mubuf.offset);
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buffer_info.globally_coherent.Assign(mubuf.glc);
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buffer_info.system_coherent.Assign(mubuf.slc);
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buffer_info.typed.Assign(is_inst_typed || is_buffer_typed);
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if (is_inst_typed) {
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const auto& mtbuf = inst.control.mtbuf;
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buffer_info.inst_data_fmt.Assign(static_cast<AmdGpu::DataFormat>(mtbuf.dfmt));
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buffer_info.inst_num_fmt.Assign(static_cast<AmdGpu::NumberFormat>(mtbuf.nfmt));
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} else {
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buffer_info.inst_data_fmt.Assign(AmdGpu::DataFormat::FormatInvalid);
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}
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const IR::Value handle =
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ir.CompositeConstruct(ir.GetScalarReg(sharp), ir.GetScalarReg(sharp + 1),
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ir.GetScalarReg(sharp + 2), ir.GetScalarReg(sharp + 3));
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const IR::VectorReg src_reg{inst.src[1].code};
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boost::container::static_vector<IR::Value, 4> comps;
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for (u32 i = 0; i < num_dwords; i++) {
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const auto src_reg_i = src_reg + i;
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if (buffer_info.typed) {
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comps.push_back(ir.GetVectorReg<IR::F32>(src_reg_i));
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} else {
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comps.push_back(ir.GetVectorReg<IR::U32>(src_reg_i));
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}
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}
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if (buffer_info.typed) {
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for (u32 i = num_dwords; i < 4; i++) {
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comps.push_back(ir.Imm32(0.f));
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}
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ir.StoreBufferFormat(handle, address, ir.CompositeConstruct(comps), buffer_info);
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} else {
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IR::Value value = num_dwords == 1 ? comps[0] : ir.CompositeConstruct(comps);
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if (scalar_width != 32) {
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value = ir.UConvert(scalar_width, IR::U32{value});
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}
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switch (scalar_width) {
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case 8:
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ir.StoreBufferU8(handle, address, IR::U8{value}, buffer_info);
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break;
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case 16:
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ir.StoreBufferU16(handle, address, IR::U16{value}, buffer_info);
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break;
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case 32:
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ir.StoreBufferU32(num_dwords, handle, address, value, buffer_info);
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break;
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default:
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UNREACHABLE();
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}
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}
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}
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template <typename T>
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void Translator::BUFFER_ATOMIC(AtomicOp op, const GcnInst& inst) {
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const auto& mubuf = inst.control.mubuf;
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const IR::VectorReg vaddr{inst.src[0].code};
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const IR::VectorReg vdata{inst.src[1].code};
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const IR::ScalarReg srsrc{inst.src[2].code * 4};
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const IR::U32 index = mubuf.idxen ? ir.GetVectorReg(vaddr) : ir.Imm32(0);
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const IR::VectorReg voffset_vgpr = mubuf.idxen ? vaddr + 1 : vaddr;
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const IR::U32 voffset = mubuf.offen ? ir.GetVectorReg(voffset_vgpr) : ir.Imm32(0);
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const IR::U32 soffset{GetSrc(inst.src[3])};
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const IR::Value address = ir.CompositeConstruct(index, voffset, soffset);
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IR::BufferInstInfo buffer_info{};
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buffer_info.index_enable.Assign(mubuf.idxen);
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buffer_info.voffset_enable.Assign(mubuf.offen);
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buffer_info.inst_offset.Assign(mubuf.offset);
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buffer_info.globally_coherent.Assign(mubuf.glc);
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buffer_info.system_coherent.Assign(mubuf.slc);
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IR::Value vdata_val = [&] {
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if constexpr (std::is_same_v<T, IR::U32>) {
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return ir.GetVectorReg<Shader::IR::U32>(vdata);
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} else if constexpr (std::is_same_v<T, IR::F32>) {
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return ir.GetVectorReg<Shader::IR::F32>(vdata);
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} else if constexpr (std::is_same_v<T, IR::U64>) {
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return ir.PackUint2x32(
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ir.CompositeConstruct(ir.GetVectorReg<Shader::IR::U32>(vdata),
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ir.GetVectorReg<Shader::IR::U32>(vdata + 1)));
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} else {
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static_assert(false, "buffer_atomic: type not supported");
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}
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}();
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const IR::Value handle =
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ir.CompositeConstruct(ir.GetScalarReg(srsrc), ir.GetScalarReg(srsrc + 1),
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ir.GetScalarReg(srsrc + 2), ir.GetScalarReg(srsrc + 3));
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const IR::Value original_val = [&] {
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switch (op) {
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case AtomicOp::Swap:
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return ir.BufferAtomicSwap(handle, address, vdata_val, buffer_info);
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case AtomicOp::CmpSwap: {
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const IR::Value cmp_val = ir.GetVectorReg(vdata + 1);
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return ir.BufferAtomicCmpSwap(handle, address, vdata_val, cmp_val, buffer_info);
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}
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case AtomicOp::Add:
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return ir.BufferAtomicIAdd(handle, address, vdata_val, buffer_info);
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case AtomicOp::Smin:
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return ir.BufferAtomicIMin(handle, address, vdata_val, true, buffer_info);
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case AtomicOp::Umin:
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return ir.BufferAtomicIMin(handle, address, vdata_val, false, buffer_info);
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case AtomicOp::Smax:
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return ir.BufferAtomicIMax(handle, address, vdata_val, true, buffer_info);
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case AtomicOp::Umax:
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return ir.BufferAtomicIMax(handle, address, vdata_val, false, buffer_info);
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case AtomicOp::And:
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return ir.BufferAtomicAnd(handle, address, vdata_val, buffer_info);
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case AtomicOp::Or:
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|
return ir.BufferAtomicOr(handle, address, vdata_val, buffer_info);
|
|
case AtomicOp::Xor:
|
|
return ir.BufferAtomicXor(handle, address, vdata_val, buffer_info);
|
|
case AtomicOp::Inc:
|
|
return ir.BufferAtomicInc(handle, address, buffer_info);
|
|
case AtomicOp::Dec:
|
|
return ir.BufferAtomicDec(handle, address, buffer_info);
|
|
case AtomicOp::Fmin:
|
|
return ir.BufferAtomicFMin(handle, address, vdata_val, buffer_info);
|
|
case AtomicOp::Fmax:
|
|
return ir.BufferAtomicFMax(handle, address, vdata_val, buffer_info);
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
}();
|
|
|
|
if (mubuf.glc) {
|
|
if constexpr (std::is_same_v<T, IR::U64>) {
|
|
UNREACHABLE();
|
|
} else {
|
|
ir.SetVectorReg(vdata, T{original_val});
|
|
}
|
|
}
|
|
}
|
|
|
|
// Image Memory
|
|
// MIMG
|
|
|
|
void Translator::IMAGE_LOAD(bool has_mip, const GcnInst& inst) {
|
|
const auto& mimg = inst.control.mimg;
|
|
IR::VectorReg addr_reg{inst.src[0].code};
|
|
IR::VectorReg dest_reg{inst.dst[0].code};
|
|
const IR::ScalarReg tsharp_reg{inst.src[2].code * 4};
|
|
|
|
const IR::Value handle = ir.GetScalarReg(tsharp_reg);
|
|
const IR::Value body =
|
|
ir.CompositeConstruct(ir.GetVectorReg(addr_reg), ir.GetVectorReg(addr_reg + 1),
|
|
ir.GetVectorReg(addr_reg + 2), ir.GetVectorReg(addr_reg + 3));
|
|
|
|
IR::TextureInstInfo info{};
|
|
info.has_lod.Assign(has_mip);
|
|
info.is_array.Assign(mimg.da);
|
|
info.is_r128.Assign(mimg.r128);
|
|
const IR::Value texel = ir.ImageRead(handle, body, {}, {}, info);
|
|
|
|
for (u32 i = 0; i < 4; i++) {
|
|
if (((mimg.dmask >> i) & 1) == 0) {
|
|
continue;
|
|
}
|
|
IR::F32 value = IR::F32{ir.CompositeExtract(texel, i)};
|
|
ir.SetVectorReg(dest_reg++, value);
|
|
}
|
|
}
|
|
|
|
void Translator::IMAGE_STORE(bool has_mip, const GcnInst& inst) {
|
|
const auto& mimg = inst.control.mimg;
|
|
IR::VectorReg addr_reg{inst.src[0].code};
|
|
IR::VectorReg data_reg{inst.dst[0].code};
|
|
const IR::ScalarReg tsharp_reg{inst.src[2].code * 4};
|
|
|
|
const IR::Value handle = ir.GetScalarReg(tsharp_reg);
|
|
const IR::Value body =
|
|
ir.CompositeConstruct(ir.GetVectorReg(addr_reg), ir.GetVectorReg(addr_reg + 1),
|
|
ir.GetVectorReg(addr_reg + 2), ir.GetVectorReg(addr_reg + 3));
|
|
|
|
IR::TextureInstInfo info{};
|
|
info.has_lod.Assign(has_mip);
|
|
info.is_array.Assign(mimg.da);
|
|
info.is_r128.Assign(mimg.r128);
|
|
|
|
boost::container::static_vector<IR::F32, 4> comps;
|
|
for (u32 i = 0; i < 4; i++) {
|
|
if (((mimg.dmask >> i) & 1) == 0) {
|
|
comps.push_back(ir.Imm32(0.f));
|
|
continue;
|
|
}
|
|
comps.push_back(ir.GetVectorReg<IR::F32>(data_reg++));
|
|
}
|
|
const IR::Value value = ir.CompositeConstruct(comps[0], comps[1], comps[2], comps[3]);
|
|
ir.ImageWrite(handle, body, {}, {}, value, info);
|
|
}
|
|
|
|
void Translator::IMAGE_GET_RESINFO(const GcnInst& inst) {
|
|
const auto& mimg = inst.control.mimg;
|
|
IR::VectorReg dst_reg{inst.dst[0].code};
|
|
const IR::ScalarReg tsharp_reg{inst.src[2].code * 4};
|
|
const auto flags = ImageResFlags(inst.control.mimg.dmask);
|
|
const bool has_mips = flags.test(ImageResComponent::MipCount);
|
|
const IR::U32 lod = ir.GetVectorReg(IR::VectorReg(inst.src[0].code));
|
|
const IR::Value tsharp = ir.GetScalarReg(tsharp_reg);
|
|
|
|
IR::TextureInstInfo info{};
|
|
info.is_array.Assign(mimg.da);
|
|
info.is_r128.Assign(mimg.r128);
|
|
|
|
const IR::Value size = ir.ImageQueryDimension(tsharp, lod, ir.Imm1(has_mips), info);
|
|
|
|
if (flags.test(ImageResComponent::Width)) {
|
|
ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 0)});
|
|
}
|
|
if (flags.test(ImageResComponent::Height)) {
|
|
ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 1)});
|
|
}
|
|
if (flags.test(ImageResComponent::Depth)) {
|
|
ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 2)});
|
|
}
|
|
if (has_mips) {
|
|
ir.SetVectorReg(dst_reg++, IR::U32{ir.CompositeExtract(size, 3)});
|
|
}
|
|
}
|
|
|
|
void Translator::IMAGE_ATOMIC(AtomicOp op, const GcnInst& inst) {
|
|
const auto& mimg = inst.control.mimg;
|
|
IR::VectorReg val_reg{inst.dst[0].code};
|
|
IR::VectorReg addr_reg{inst.src[0].code};
|
|
const IR::ScalarReg tsharp_reg{inst.src[2].code * 4};
|
|
|
|
IR::TextureInstInfo info{};
|
|
info.is_array.Assign(mimg.da);
|
|
info.is_r128.Assign(mimg.r128);
|
|
|
|
const IR::Value value = ir.GetVectorReg(val_reg);
|
|
const IR::Value handle = ir.GetScalarReg(tsharp_reg);
|
|
const IR::Value body =
|
|
ir.CompositeConstruct(ir.GetVectorReg(addr_reg), ir.GetVectorReg(addr_reg + 1),
|
|
ir.GetVectorReg(addr_reg + 2), ir.GetVectorReg(addr_reg + 3));
|
|
const IR::Value prev = [&] {
|
|
switch (op) {
|
|
case AtomicOp::Swap:
|
|
return ir.ImageAtomicExchange(handle, body, value, {});
|
|
case AtomicOp::CmpSwap: {
|
|
const IR::Value cmp_val = ir.GetVectorReg(val_reg + 1);
|
|
return ir.ImageAtomicCmpSwap(handle, body, value, cmp_val, info);
|
|
}
|
|
case AtomicOp::Add:
|
|
return ir.ImageAtomicIAdd(handle, body, value, info);
|
|
case AtomicOp::Smin:
|
|
return ir.ImageAtomicIMin(handle, body, value, true, info);
|
|
case AtomicOp::Umin:
|
|
return ir.ImageAtomicUMin(handle, body, value, info);
|
|
case AtomicOp::Smax:
|
|
return ir.ImageAtomicIMax(handle, body, value, true, info);
|
|
case AtomicOp::Umax:
|
|
return ir.ImageAtomicUMax(handle, body, value, info);
|
|
case AtomicOp::Fmax:
|
|
return ir.ImageAtomicFMax(handle, body, value, info);
|
|
case AtomicOp::Fmin:
|
|
return ir.ImageAtomicFMin(handle, body, value, info);
|
|
case AtomicOp::And:
|
|
return ir.ImageAtomicAnd(handle, body, value, info);
|
|
case AtomicOp::Or:
|
|
return ir.ImageAtomicOr(handle, body, value, info);
|
|
case AtomicOp::Xor:
|
|
return ir.ImageAtomicXor(handle, body, value, info);
|
|
case AtomicOp::Inc:
|
|
return ir.ImageAtomicInc(handle, body, value, info);
|
|
case AtomicOp::Dec:
|
|
return ir.ImageAtomicDec(handle, body, value, info);
|
|
default:
|
|
UNREACHABLE();
|
|
}
|
|
}();
|
|
if (mimg.glc) {
|
|
ir.SetVectorReg(val_reg, IR::U32{prev});
|
|
}
|
|
}
|
|
|
|
IR::Value EmitImageSample(IR::IREmitter& ir, const GcnInst& inst, const IR::ScalarReg tsharp_reg,
|
|
const IR::ScalarReg sampler_reg, const IR::VectorReg addr_reg,
|
|
bool gather, u32 pc) {
|
|
const auto& mimg = inst.control.mimg;
|
|
const auto flags = MimgModifierFlags(mimg.mod);
|
|
|
|
IR::TextureInstInfo info{};
|
|
info.is_depth.Assign(flags.test(MimgModifier::Pcf));
|
|
info.has_bias.Assign(flags.test(MimgModifier::LodBias));
|
|
info.has_lod_clamp.Assign(flags.test(MimgModifier::LodClamp));
|
|
info.force_level0.Assign(flags.test(MimgModifier::Level0));
|
|
info.has_offset.Assign(flags.test(MimgModifier::Offset));
|
|
info.has_lod.Assign(flags.any(MimgModifier::Lod));
|
|
info.is_array.Assign(mimg.da);
|
|
info.is_unnormalized.Assign(mimg.unrm);
|
|
info.is_r128.Assign(mimg.r128);
|
|
info.pc.Assign(pc);
|
|
|
|
if (gather) {
|
|
info.gather_comp.Assign(std::bit_width(mimg.dmask) - 1);
|
|
info.is_gather.Assign(true);
|
|
} else {
|
|
info.has_derivatives.Assign(flags.test(MimgModifier::Derivative));
|
|
}
|
|
|
|
// Load first dword of T# and the full S#. We will use them as the handle that will guide
|
|
// resource tracking pass where to read the sharps. This will later also get patched to the
|
|
// backend texture binding index.
|
|
const IR::Value image_handle = ir.GetScalarReg(tsharp_reg);
|
|
const IR::Value sampler_handle =
|
|
ir.CompositeConstruct(ir.GetScalarReg(sampler_reg), ir.GetScalarReg(sampler_reg + 1),
|
|
ir.GetScalarReg(sampler_reg + 2), ir.GetScalarReg(sampler_reg + 3));
|
|
|
|
// Determine how many address registers need to be passed.
|
|
// The image type is unknown, so add all 4 possible base registers and resolve later.
|
|
int num_addr_regs = 4;
|
|
if (info.has_offset) {
|
|
++num_addr_regs;
|
|
}
|
|
if (info.has_bias) {
|
|
++num_addr_regs;
|
|
}
|
|
if (info.is_depth) {
|
|
++num_addr_regs;
|
|
}
|
|
if (info.has_derivatives) {
|
|
// The image type is unknown, so add all 6 possible derivative registers and resolve later.
|
|
num_addr_regs += 6;
|
|
}
|
|
|
|
// Fetch all the address registers to pass in the IR instruction. There can be up to 13
|
|
// registers.
|
|
const auto get_addr_reg = [&](int index) -> IR::F32 {
|
|
if (index >= num_addr_regs) {
|
|
return ir.Imm32(0.f);
|
|
}
|
|
return ir.GetVectorReg<IR::F32>(addr_reg + index);
|
|
};
|
|
const IR::Value address1 =
|
|
ir.CompositeConstruct(get_addr_reg(0), get_addr_reg(1), get_addr_reg(2), get_addr_reg(3));
|
|
const IR::Value address2 =
|
|
ir.CompositeConstruct(get_addr_reg(4), get_addr_reg(5), get_addr_reg(6), get_addr_reg(7));
|
|
const IR::Value address3 =
|
|
ir.CompositeConstruct(get_addr_reg(8), get_addr_reg(9), get_addr_reg(10), get_addr_reg(11));
|
|
const IR::Value address4 = get_addr_reg(12);
|
|
|
|
// Issue the placeholder IR instruction.
|
|
IR::Value texel = ir.ImageSampleRaw(image_handle, sampler_handle, address1, address2, address3,
|
|
address4, info);
|
|
if (info.is_depth && !gather) {
|
|
// For non-gather depth sampling, only return a single value.
|
|
texel = ir.CompositeExtract(texel, 0);
|
|
}
|
|
return texel;
|
|
}
|
|
|
|
void Translator::IMAGE_SAMPLE(const GcnInst& inst) {
|
|
const auto& mimg = inst.control.mimg;
|
|
IR::VectorReg addr_reg{inst.src[0].code};
|
|
IR::VectorReg dest_reg{inst.dst[0].code};
|
|
const IR::ScalarReg tsharp_reg{inst.src[2].code * 4};
|
|
const IR::ScalarReg sampler_reg{inst.src[3].code * 4};
|
|
const auto flags = MimgModifierFlags(mimg.mod);
|
|
|
|
const IR::Value texel = EmitImageSample(ir, inst, tsharp_reg, sampler_reg, addr_reg, false, pc);
|
|
for (u32 i = 0; i < 4; i++) {
|
|
if (((mimg.dmask >> i) & 1) == 0) {
|
|
continue;
|
|
}
|
|
IR::F32 value;
|
|
if (flags.test(MimgModifier::Pcf)) {
|
|
value = i < 3 ? IR::F32{texel} : ir.Imm32(1.0f);
|
|
} else {
|
|
value = IR::F32{ir.CompositeExtract(texel, i)};
|
|
}
|
|
ir.SetVectorReg(dest_reg++, value);
|
|
}
|
|
}
|
|
|
|
void Translator::IMAGE_GATHER(const GcnInst& inst) {
|
|
const auto& mimg = inst.control.mimg;
|
|
IR::VectorReg addr_reg{inst.src[0].code};
|
|
IR::VectorReg dest_reg{inst.dst[0].code};
|
|
const IR::ScalarReg tsharp_reg{inst.src[2].code * 4};
|
|
const IR::ScalarReg sampler_reg{inst.src[3].code * 4};
|
|
const auto flags = MimgModifierFlags(mimg.mod);
|
|
|
|
// For gather4 instructions dmask selects which component to read and must have
|
|
// only one bit set to 1
|
|
ASSERT_MSG(std::popcount(mimg.dmask) == 1, "Unexpected bits in gather dmask");
|
|
// should be always 1st (R) component for depth
|
|
ASSERT(!flags.test(MimgModifier::Pcf) || mimg.dmask & 1);
|
|
|
|
const IR::Value texel = EmitImageSample(ir, inst, tsharp_reg, sampler_reg, addr_reg, true, pc);
|
|
for (u32 i = 0; i < 4; i++) {
|
|
const IR::F32 value = IR::F32{ir.CompositeExtract(texel, i)};
|
|
ir.SetVectorReg(dest_reg++, value);
|
|
}
|
|
}
|
|
|
|
void Translator::IMAGE_GET_LOD(const GcnInst& inst) {
|
|
const auto& mimg = inst.control.mimg;
|
|
IR::VectorReg dst_reg{inst.dst[0].code};
|
|
IR::VectorReg addr_reg{inst.src[0].code};
|
|
const IR::ScalarReg tsharp_reg{inst.src[2].code * 4};
|
|
|
|
IR::TextureInstInfo info{};
|
|
info.is_array.Assign(mimg.da);
|
|
info.is_r128.Assign(mimg.r128);
|
|
|
|
const IR::Value handle = ir.GetScalarReg(tsharp_reg);
|
|
const IR::Value body = ir.CompositeConstruct(
|
|
ir.GetVectorReg<IR::F32>(addr_reg), ir.GetVectorReg<IR::F32>(addr_reg + 1),
|
|
ir.GetVectorReg<IR::F32>(addr_reg + 2), ir.GetVectorReg<IR::F32>(addr_reg + 3));
|
|
const IR::Value lod = ir.ImageQueryLod(handle, body, info);
|
|
ir.SetVectorReg(dst_reg++, IR::F32{ir.CompositeExtract(lod, 0)});
|
|
ir.SetVectorReg(dst_reg++, IR::F32{ir.CompositeExtract(lod, 1)});
|
|
}
|
|
|
|
} // namespace Shader::Gcn
|