mirror of
https://github.com/shadps4-emu/shadPS4.git
synced 2026-04-09 11:11:29 -06:00
avoid using u64 emmiter
This commit is contained in:
georgemoralis
parent
6ea8587826
commit
17b38edeb5
@ -1136,108 +1136,117 @@ void Translator::V_CMP_U32(ConditionOp op, bool is_signed, bool set_exec, const
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}
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void Translator::V_CMP_U64(ConditionOp op, bool is_signed, bool set_exec, const GcnInst& inst) {
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const IR::U64 src0 = [&]() -> IR::U64 {
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switch (inst.src[0].field) {
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case OperandField::ScalarGPR: {
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IR::U32 low = ir.GetScalarReg(IR::ScalarReg(inst.src[0].code));
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IR::U32 high = ir.GetScalarReg(IR::ScalarReg(inst.src[0].code + 1));
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return ir.PackUint2x32(ir.CompositeConstruct(low, high));
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}
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case OperandField::VectorGPR: {
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IR::U32 low = ir.GetVectorReg(IR::VectorReg(inst.src[0].code));
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IR::U32 high = ir.GetVectorReg(IR::VectorReg(inst.src[0].code + 1));
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return ir.PackUint2x32(ir.CompositeConstruct(low, high));
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}
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case OperandField::VccLo: {
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IR::U1 vcc_bit = ir.GetVcc();
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IR::Value vcc_val =
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ir.Select(vcc_bit, ir.Imm64(static_cast<u64>(-1)), ir.Imm64(static_cast<u64>(0)));
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return IR::U64{vcc_val};
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}
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case OperandField::ConstZero:
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return ir.Imm64(static_cast<u64>(0));
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case OperandField::SignedConstIntPos:
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return ir.Imm64(static_cast<u64>(inst.src[0].code));
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case OperandField::SignedConstIntNeg: {
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s32 decoded_value = -s32(inst.src[0].code) + SignedConstIntNegMin - 1;
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return ir.Imm64(static_cast<u64>(decoded_value));
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}
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default:
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UNREACHABLE_MSG("src0 = {}", u32(inst.src[0].field));
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}
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}();
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ASSERT(!is_signed);
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const IR::U64 src1 = [&]() -> IR::U64 {
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switch (inst.src[1].field) {
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case OperandField::ScalarGPR: {
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IR::U32 low = ir.GetScalarReg(IR::ScalarReg(inst.src[1].code));
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IR::U32 high = ir.GetScalarReg(IR::ScalarReg(inst.src[1].code + 1));
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return ir.PackUint2x32(ir.CompositeConstruct(low, high));
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}
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case OperandField::VectorGPR: {
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IR::U32 low = ir.GetVectorReg(IR::VectorReg(inst.src[1].code));
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IR::U32 high = ir.GetVectorReg(IR::VectorReg(inst.src[1].code + 1));
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return ir.PackUint2x32(ir.CompositeConstruct(low, high));
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}
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case OperandField::VccLo: {
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IR::U1 vcc_bit = ir.GetVcc();
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IR::Value vcc_val =
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ir.Select(vcc_bit, ir.Imm64(static_cast<u64>(-1)), ir.Imm64(static_cast<u64>(0)));
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return IR::U64{vcc_val};
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}
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case OperandField::ConstZero:
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return ir.Imm64(static_cast<u64>(0));
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case OperandField::SignedConstIntPos:
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return ir.Imm64(static_cast<u64>(inst.src[1].code));
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case OperandField::SignedConstIntNeg: {
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s32 decoded_value = -s32(inst.src[1].code) + SignedConstIntNegMin - 1;
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return ir.Imm64(static_cast<u64>(decoded_value));
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}
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default:
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UNREACHABLE_MSG("Unsupported src[1] operand field: {}", u32(inst.src[1].field));
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}
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}();
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// Lambda to read a 64-bit operand as two 32-bit parts
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auto read_u64 = [&](const InstOperand& op, bool is_src0) -> std::pair<IR::U32, IR::U32> {
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using enum OperandField;
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// Perform the 64-bit comparison
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const IR::U1 result = [&] {
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switch (op) {
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case ConditionOp::EQ:
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return ir.IEqual(src0, src1);
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case ConditionOp::LG: // NE
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return ir.INotEqual(src0, src1);
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case ConditionOp::GT:
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return ir.IGreaterThan(src0, src1, false); // false = unsigned
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case ConditionOp::LT:
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return ir.ILessThan(src0, src1, false);
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case ConditionOp::GE:
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return ir.IGreaterThanEqual(src0, src1, false);
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case ConditionOp::LE:
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return ir.ILessThanEqual(src0, src1, false);
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default:
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UNREACHABLE_MSG("Unsupported V_CMP_U64 condition operation: {}", u32(op));
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switch (op.field) {
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case ScalarGPR:
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return {ir.GetScalarReg(IR::ScalarReg(op.code)),
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ir.GetScalarReg(IR::ScalarReg(op.code + 1))};
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case VectorGPR:
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return {ir.GetVectorReg(IR::VectorReg(op.code)),
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ir.GetVectorReg(IR::VectorReg(op.code + 1))};
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case ConstZero:
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return {ir.Imm32(0), ir.Imm32(0)};
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case SignedConstIntPos:
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return {ir.Imm32(op.code), ir.Imm32(0)};
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case SignedConstIntNeg: {
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s32 v = -s32(op.code) + SignedConstIntNegMin - 1;
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return {ir.Imm32(v), ir.Imm32(v < 0 ? -1 : 0)};
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}
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}();
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case VccLo:
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// treat as 32-bit values, zero-extend to 64-bit
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{
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IR::U32 val = ir.GetScalarReg(IR::ScalarReg(op.code));
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return {val, ir.Imm32(0)};
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}
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default:
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UNREACHABLE_MSG("Unsupported operand field {}", u32(op.field));
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}
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};
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const auto [a_lo, a_hi] = read_u64(inst.src[0], true);
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const auto [b_lo, b_hi] = read_u64(inst.src[1], false);
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IR::U1 cmp_result{};
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switch (op) {
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case ConditionOp::EQ: {
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IR::U1 hi_eq = ir.IEqual(a_hi, b_hi);
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IR::U1 lo_eq = ir.IEqual(a_lo, b_lo);
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cmp_result = ir.LogicalAnd(hi_eq, lo_eq);
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break;
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}
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case ConditionOp::LG: { // NE
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IR::U1 hi_ne = ir.INotEqual(a_hi, b_hi);
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IR::U1 lo_ne = ir.INotEqual(a_lo, b_lo);
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cmp_result = ir.LogicalOr(hi_ne, lo_ne);
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break;
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}
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case ConditionOp::GT: {
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IR::U1 hi_gt = ir.IGreaterThan(a_hi, b_hi, false);
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IR::U1 hi_eq = ir.IEqual(a_hi, b_hi);
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IR::U1 lo_gt = ir.IGreaterThan(a_lo, b_lo, false);
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cmp_result = ir.LogicalOr(hi_gt, ir.LogicalAnd(hi_eq, lo_gt));
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break;
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}
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case ConditionOp::LT: {
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IR::U1 hi_lt = ir.ILessThan(a_hi, b_hi, false);
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IR::U1 hi_eq = ir.IEqual(a_hi, b_hi);
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IR::U1 lo_lt = ir.ILessThan(a_lo, b_lo, false);
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cmp_result = ir.LogicalOr(hi_lt, ir.LogicalAnd(hi_eq, lo_lt));
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break;
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}
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case ConditionOp::GE: {
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IR::U1 hi_gt = ir.IGreaterThan(a_hi, b_hi, false);
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IR::U1 hi_eq = ir.IEqual(a_hi, b_hi);
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IR::U1 lo_ge = ir.IGreaterThanEqual(a_lo, b_lo, false);
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cmp_result = ir.LogicalOr(hi_gt, ir.LogicalAnd(hi_eq, lo_ge));
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break;
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}
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case ConditionOp::LE: {
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IR::U1 hi_lt = ir.ILessThan(a_hi, b_hi, false);
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IR::U1 hi_eq = ir.IEqual(a_hi, b_hi);
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IR::U1 lo_le = ir.ILessThanEqual(a_lo, b_lo, false);
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cmp_result = ir.LogicalOr(hi_lt, ir.LogicalAnd(hi_eq, lo_le));
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break;
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}
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default:
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UNREACHABLE_MSG("Unsupported V_CMP_U64 condition {}", u32(op));
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}
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// Handle flags
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if (is_signed) {
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UNREACHABLE_MSG("V_CMP_U64 with signed integers is not supported");
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}
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if (set_exec) {
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UNREACHABLE_MSG("Exec setting for V_CMP_U64 is not supported");
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}
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// Write result (1-bit boolean) to destination
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switch (inst.dst[1].field) {
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case OperandField::VccLo:
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return ir.SetVcc(result);
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ir.SetVcc(cmp_result);
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break;
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case OperandField::ScalarGPR:
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return ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[1].code), result);
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case OperandField::VectorGPR: {
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IR::Value result_val = ir.Select(result, ir.Imm32(1), ir.Imm32(0));
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ir.SetVectorReg(IR::VectorReg(inst.dst[1].code), IR::U32{result_val});
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} break;
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ir.SetThreadBitScalarReg(IR::ScalarReg(inst.dst[1].code), cmp_result);
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break;
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default:
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UNREACHABLE_MSG("Unsupported dst field: {}", u32(inst.dst[1].field));
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UNREACHABLE_MSG("Invalid V_CMP_U64 destination");
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}
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}
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