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https://github.com/shadps4-emu/shadPS4.git
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VOP3P instructions definitions
This commit is contained in:
Marcin Mikołajczyk
parent
969955b8a0
commit
de2f69a4d2
@ -3,6 +3,7 @@
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#include <algorithm>
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#include "common/assert.h"
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#include "core/libraries/kernel/process.h"
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#include "shader_recompiler/frontend/decode.h"
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#include <magic_enum/magic_enum.hpp>
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@ -39,6 +40,7 @@ InstEncoding GetInstructionEncoding(u32 token) {
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encoding = static_cast<InstEncoding>(token & (u32)EncodingMask::MASK_6bit);
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switch (encoding) {
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case InstEncoding::VOP3:
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case InstEncoding::VOP3P:
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case InstEncoding::EXP:
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case InstEncoding::VINTRP:
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case InstEncoding::DS:
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@ -82,7 +84,6 @@ InstEncoding GetInstructionEncoding(u32 token) {
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break;
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}
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UNREACHABLE();
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return InstEncoding::ILLEGAL;
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}
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@ -111,7 +112,7 @@ GcnInst GcnDecodeContext::decodeInstruction(GcnCodeSlice& code) {
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const uint32_t token = code.at(0);
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InstEncoding encoding = GetInstructionEncoding(token);
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ASSERT_MSG(encoding != InstEncoding::ILLEGAL, "illegal encoding");
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ASSERT_MSG(encoding != InstEncoding::ILLEGAL, "illegal encoding: {:#x}", token);
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uint32_t encodingLen = getEncodingLength(encoding);
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// Clear the instruction
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@ -155,6 +156,7 @@ uint32_t GcnDecodeContext::getEncodingLength(InstEncoding encoding) {
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break;
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case InstEncoding::VOP3:
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case InstEncoding::VOP3P:
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case InstEncoding::MUBUF:
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case InstEncoding::MTBUF:
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case InstEncoding::MIMG:
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@ -189,6 +191,9 @@ uint32_t GcnDecodeContext::getOpMapOffset(InstEncoding encoding) {
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case InstEncoding::VOP3:
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offset = (uint32_t)OpcodeMap::OP_MAP_VOP3;
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break;
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case InstEncoding::VOP3P:
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offset = (uint32_t)OpcodeMap::OP_MAP_VOP3P;
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break;
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case InstEncoding::EXP:
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offset = (uint32_t)OpcodeMap::OP_MAP_EXP;
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break;
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@ -381,6 +386,9 @@ void GcnDecodeContext::decodeInstruction64(InstEncoding encoding, GcnCodeSlice&
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case InstEncoding::VOP3:
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decodeInstructionVOP3(hexInstruction);
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break;
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case InstEncoding::VOP3P:
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decodeInstructionVOP3P(hexInstruction);
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break;
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case InstEncoding::MUBUF:
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decodeInstructionMUBUF(hexInstruction);
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break;
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@ -712,6 +720,55 @@ void GcnDecodeContext::decodeInstructionVOP3(uint64_t hexInstruction) {
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}
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}
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void GcnDecodeContext::decodeInstructionVOP3P(uint64_t hexInstruction) {
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u32 vdst = bit::extract(hexInstruction, 7, 0);
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u32 op = bit::extract(hexInstruction, 22, 16);
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u32 src0 = bit::extract(hexInstruction, 40, 32);
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u32 src1 = bit::extract(hexInstruction, 49, 41);
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u32 src2 = bit::extract(hexInstruction, 58, 50);
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m_instruction.opcode = static_cast<Opcode>(op + static_cast<u32>(OpcodeMap::OP_MAP_VOP3P));
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m_instruction.src[0].field = getOperandField(src0);
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m_instruction.src[0].code =
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m_instruction.src[0].field == OperandField::VectorGPR ? src0 - VectorGPRMin : src0;
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m_instruction.src[1].field = getOperandField(src1);
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m_instruction.src[1].code =
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m_instruction.src[1].field == OperandField::VectorGPR ? src1 - VectorGPRMin : src1;
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m_instruction.src[2].field = getOperandField(src2);
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m_instruction.src[2].code =
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m_instruction.src[2].field == OperandField::VectorGPR ? src2 - VectorGPRMin : src2;
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m_instruction.dst[0].field = OperandField::VectorGPR;
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m_instruction.dst[0].code = vdst;
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m_instruction.control.vop3p = *reinterpret_cast<InstControlVOP3P*>(&hexInstruction);
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// update input modifier
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auto& control = m_instruction.control.vop3p;
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for (u32 i = 0; i != 3; ++i) {
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if (control.neg & (1u << i)) {
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m_instruction.src[i].input_modifier.neg = true;
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}
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if (control.neg_hi & (1u << i)) {
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m_instruction.src[i].input_modifier.neg_hi = true;
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}
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if (control.op_sel & (1u << i)) {
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m_instruction.src[i].op_sel.op_sel = true;
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}
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if (control.get_op_sel_hi(i)) {
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m_instruction.src[i].op_sel.op_sel_hi = true;
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}
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}
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// update output modifier
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auto& outputMod = m_instruction.dst[0].output_modifier;
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outputMod.clamp = static_cast<bool>(control.clamp);
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}
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void GcnDecodeContext::decodeInstructionMUBUF(uint64_t hexInstruction) {
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u32 op = bit::extract(hexInstruction, 24, 18);
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u32 vaddr = bit::extract(hexInstruction, 39, 32);
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@ -84,6 +84,7 @@ private:
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void decodeInstructionVINTRP(uint32_t hexInstruction);
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// 64 bits encodings
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void decodeInstructionVOP3(uint64_t hexInstruction);
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void decodeInstructionVOP3P(uint64_t hexInstruction);
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void decodeInstructionMUBUF(uint64_t hexInstruction);
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void decodeInstructionMTBUF(uint64_t hexInstruction);
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void decodeInstructionMIMG(uint64_t hexInstruction);
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@ -1784,6 +1784,88 @@ constexpr std::array<InstFormat, 455> InstructionFormatVOP3 = {{
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{},
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}};
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constexpr std::array<InstFormat, 35> InstructionFormatVOP3P = {{
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// 0 = V_PK_MAD_I16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 3, 1, ScalarType::Sint16,
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ScalarType::Sint16},
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// 1 = V_PK_MUL_LO_U16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 2, 1, ScalarType::Uint16,
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ScalarType::Uint16},
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// 2 = V_PK_ADD_I16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 2, 1, ScalarType::Sint16,
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ScalarType::Sint16},
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// 3 = V_PK_SUB_I16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 2, 1, ScalarType::Sint16,
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ScalarType::Sint16},
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// 4 = V_PK_LSHLREV_B16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 2, 1, ScalarType::Uint16,
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ScalarType::Uint16},
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// 5 = V_PK_LSHRREV_B16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 2, 1, ScalarType::Uint16,
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ScalarType::Uint16},
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// 6 = V_PK_ASHRREV_I16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 2, 1, ScalarType::Sint16,
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ScalarType::Uint16},
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// 7 = V_PK_MAX_I16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 2, 1, ScalarType::Sint16,
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ScalarType::Sint16},
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// 8 = V_PK_MIN_I16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 2, 1, ScalarType::Sint16,
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ScalarType::Sint16},
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// 9 = V_PK_MAD_U16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 3, 1, ScalarType::Uint16,
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ScalarType::Uint16},
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// 10 = V_PK_ADD_U16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 2, 1, ScalarType::Uint16,
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ScalarType::Uint16},
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// 11 = V_PK_SUB_U16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 2, 1, ScalarType::Uint16,
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ScalarType::Uint16},
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// 12 = V_PK_MAX_U16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 2, 1, ScalarType::Uint16,
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ScalarType::Uint16},
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// 13 = V_PK_MIN_U16
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{InstClass::VectorIntArith16, InstCategory::VectorALU, 2, 1, ScalarType::Uint16,
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ScalarType::Uint16},
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// 14 = V_PK_FMA_F16
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{InstClass::VectorFpArith16, InstCategory::VectorALU, 3, 1, ScalarType::Float16,
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ScalarType::Float16},
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// 15 = V_PK_ADD_F16
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{InstClass::VectorFpArith16, InstCategory::VectorALU, 2, 1, ScalarType::Float16,
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ScalarType::Float16},
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// 16 = V_PK_MUL_F16
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{InstClass::VectorFpArith16, InstCategory::VectorALU, 2, 1, ScalarType::Float16,
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ScalarType::Float16},
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// 17 = V_PK_MIN_F16
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{InstClass::VectorFpArith16, InstCategory::VectorALU, 2, 1, ScalarType::Float16,
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ScalarType::Float16},
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// 18 = V_PK_MAX_F16
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{InstClass::VectorFpArith16, InstCategory::VectorALU, 2, 1, ScalarType::Float16,
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ScalarType::Float16},
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{},
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{},
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{},
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{},
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{},
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{},
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{},
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{},
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{},
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{},
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{},
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{},
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{},
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// 32 = V_MAD_MIX_F32
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{InstClass::VectorFpArith32, InstCategory::VectorALU, 3, 1, ScalarType::Float32,
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ScalarType::Float32},
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// 33 = V_MAD_MIXLO_F16
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{InstClass::VectorFpArith32, InstCategory::VectorALU, 3, 1, ScalarType::Float32,
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ScalarType::Float32},
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// 34 = V_MAD_MIXHI_F16
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{InstClass::VectorFpArith32, InstCategory::VectorALU, 3, 1, ScalarType::Float32,
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ScalarType::Float32},
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}};
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constexpr std::array<InstFormat, 71> InstructionFormatVOP1 = {{
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// 0 = V_NOP
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{InstClass::VectorMisc, InstCategory::VectorALU, 0, 1, ScalarType::Any, ScalarType::Any},
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@ -3705,6 +3787,8 @@ InstFormat InstructionFormat(InstEncoding encoding, uint32_t opcode) {
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return InstructionFormatVOPC[opcode];
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case InstEncoding::VOP3:
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return InstructionFormatVOP3[opcode];
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case InstEncoding::VOP3P:
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return InstructionFormatVOP3P[opcode];
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case InstEncoding::EXP:
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return InstructionFormatEXP[opcode];
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case InstEncoding::VINTRP:
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@ -3,6 +3,7 @@
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#pragma once
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#include "common/assert.h"
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#include "shader_recompiler/frontend/opcodes.h"
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namespace Shader::Gcn {
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@ -25,6 +26,7 @@ enum OperandFieldRange {
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/// These are applied after loading an operand register.
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struct InputModifiers {
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bool neg = false;
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bool neg_hi = false;
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bool abs = false;
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};
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@ -34,11 +36,18 @@ struct OutputModifiers {
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float multiplier = 0.f;
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};
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struct OperandSelection {
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bool op_sel = false;
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bool op_sel_hi = false;
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};
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struct InstOperand {
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OperandField field = OperandField::Undefined;
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ScalarType type = ScalarType::Undefined;
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InputModifiers input_modifier = {};
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OutputModifiers output_modifier = {};
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// only valid for packed 16bit operations
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OperandSelection op_sel = {};
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u32 code = 0xFFFFFFFF;
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};
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@ -90,6 +99,32 @@ struct InstControlVOP3 {
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u64 neg : 3;
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};
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struct InstControlVOP3P {
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u64 : 8;
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u64 neg_hi : 3;
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u64 op_sel : 3;
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u64 op_sel_hi_2 : 1;
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u64 clamp : 1;
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u64 : 43;
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u64 op_sel_hi_01 : 2;
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u64 neg : 3;
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bool get_op_sel_hi(int idx) {
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switch (idx) {
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case 0:
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return (op_sel_hi_01 & 1) == 1;
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case 1:
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return ((op_sel_hi_01 >> 1) & 1) == 1;
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case 2:
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return (op_sel_hi_2 & 1) == 1;
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default:
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UNREACHABLE_MSG("get_op_sel_hi: {}", idx);
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}
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}
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};
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static_assert(sizeof(InstControlVOP3P) == 8);
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struct InstControlSMRD {
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u32 offset : 8;
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u32 imm : 1;
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@ -174,6 +209,7 @@ union InstControl {
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InstControlSOPK sopk;
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InstControlSOPP sopp;
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InstControlVOP3 vop3;
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InstControlVOP3P vop3p;
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InstControlSMRD smrd;
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InstControlMUBUF mubuf;
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InstControlMTBUF mtbuf;
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@ -662,6 +662,33 @@ enum class OpcodeVOP3 : u32 {
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OP_RANGE_VOP3 = V_EXP_LEGACY_F32 + 1,
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};
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enum class OpcodeVOP3P : u32 {
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V_PK_MAD_I16 = 0,
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V_PK_MUL_LO_U16 = 1,
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V_PK_ADD_I16 = 2,
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V_PK_SUB_I16 = 3,
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V_PK_LSHLREV_B16 = 4,
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V_PK_LSHRREV_B16 = 5,
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V_PK_ASHRREV_I16 = 6,
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V_PK_MAX_I16 = 7,
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V_PK_MIN_I16 = 8,
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V_PK_MAD_U16 = 9,
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V_PK_ADD_U16 = 10,
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V_PK_SUB_U16 = 11,
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V_PK_MAX_U16 = 12,
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V_PK_MIN_U16 = 13,
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V_PK_FMA_F16 = 14,
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V_PK_ADD_F16 = 15,
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V_PK_MUL_F16 = 16,
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V_PK_MIN_F16 = 17,
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V_PK_MAX_F16 = 18,
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V_MAD_MIX_F32 = 32,
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V_MAD_MIXLO_F16 = 33,
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V_MAD_MIXHI_F16 = 34,
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OP_RANGE_VOP3P = V_MAD_MIXHI_F16 + 1,
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};
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enum class OpcodeVOP1 : u32 {
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V_NOP = 0,
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V_MOV_B32 = 1,
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@ -1313,6 +1340,7 @@ enum class OpcodeMap : u32 {
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OP_MAP_MTBUF = OP_MAP_MUBUF + (u32)OpcodeMUBUF::OP_RANGE_MUBUF,
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OP_MAP_MIMG = OP_MAP_MTBUF + (u32)OpcodeMTBUF::OP_RANGE_MTBUF,
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OP_MAP_EXP = OP_MAP_MIMG + (u32)OpcodeMIMG::OP_RANGE_MIMG,
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OP_MAP_VOP3P = OP_MAP_EXP + (u32)OpcodeEXP::OP_RANGE_EXP,
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};
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enum class Opcode : u32 {
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@ -2192,6 +2220,29 @@ enum class Opcode : u32 {
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IMAGE_SAMPLE_C_CD_CL_O = 111 + (u32)OpcodeMap::OP_MAP_MIMG,
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// EXP
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EXP = 0 + (u32)OpcodeMap::OP_MAP_EXP,
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// VOP3P
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V_PK_MAD_I16 = 0 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_MUL_LO_U16 = 1 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_ADD_I16 = 2 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_SUB_I16 = 3 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_LSHLREV_B16 = 4 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_LSHRREV_B16 = 5 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_ASHRREV_I16 = 6 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_MAX_I16 = 7 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_MIN_I16 = 8 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_MAD_U16 = 9 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_ADD_U16 = 10 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_SUB_U16 = 11 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_MAX_U16 = 12 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_MIN_U16 = 13 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_FMA_F16 = 14 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_ADD_F16 = 15 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_MUL_F16 = 16 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_MIN_F16 = 17 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_PK_MAX_F16 = 18 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_MAD_MIX_F32 = 32 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_MAD_MIXLO_F16 = 33 + (u32)OpcodeMap::OP_MAP_VOP3P,
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V_MAD_MIXHI_F16 = 34 + (u32)OpcodeMap::OP_MAP_VOP3P,
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};
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enum class EncodingMask : u32 {
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@ -2222,6 +2273,8 @@ enum class InstEncoding : u32 {
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VOP3 = 0x00000034u << 26,
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/// bits [31:26] - (1 1 1 1 1 0)
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EXP = 0x0000003Eu << 26,
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/// bits [31:26] - (1 1 0 0 1 1)
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VOP3P = 0x00000033u << 26,
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/// bits [31:26] - (1 1 0 0 1 0)
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VINTRP = 0x00000032u << 26,
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/// bits [31:26] - (1 1 0 1 1 0)
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@ -2271,6 +2324,7 @@ enum class InstClass : u32 {
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VectorBitField32,
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VectorThreadMask,
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VectorBitField64,
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VectorFpArith16,
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VectorFpArith32,
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VectorFpRound32,
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VectorFpField32,
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@ -2281,6 +2335,7 @@ enum class InstClass : u32 {
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VectorFpField64,
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VectorFpTran64,
|
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VectorFpCmp64,
|
||||
VectorIntArith16,
|
||||
VectorIntArith32,
|
||||
VectorIntArith64,
|
||||
VectorIntCmp32,
|
||||
@ -2360,8 +2415,10 @@ enum class InstCategory : u32 {
|
||||
enum class ScalarType : u32 {
|
||||
Undefined,
|
||||
Any,
|
||||
Uint16,
|
||||
Uint32,
|
||||
Uint64,
|
||||
Sint16,
|
||||
Sint32,
|
||||
Sint64,
|
||||
Float16,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user